Arithmetic logic unit dequantization

Details Arithmetic logic unit dequantization Arithmetic logic unit dequantization

1992-11-24

1994-09-20

Malzahn, David H.

Boots, shoes, and leggings

382 56, G06K 936

Patent

active

053495454

ABSTRACT:
A device for dequantizing signals is provided in which two hardware operations are generated. The first hardware operation generates a signal representative of a binary function s(a,b) wherein the input signal b is shifted, incremented and decremented to provide signals 2b+1, 2b and 2b-1. A selector selects the first of these signals when a is positive, the second when a is zero, and the third when a is negative. The second signal generated is representative of a unary function t(c). In this function signal c is incremented and decremented to provide signals c-1, c and c+1. A selector selects the first of these signals when c is positive, the second when c is zero, and the third when c is negative. The selected signal in the unary operation is applied to a further selector which also receives signal c as an input. One of the two signals applied to the further selector is selected according to whether signal c is odd or even. Signals s(a,b) and t(c) are then combined by applying the signal s(a,b) to the c input of t(c) to implement the conventional dequantization formula d=Q*(2*v+ sign(v)) if d is even d=d-sign(d).

REFERENCES:
patent: 4698689 (1987-10-01), Tzou
patent: 4807298 (1989-02-01), Conte et al.
patent: 5054103 (1991-10-01), Yasuda et al.

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