Arithmetic logic unit circuit with reduced propagation delays

Details Arithmetic logic unit circuit with reduced propagation delays Arithmetic logic unit circuit with reduced propagation delays

1996-04-03

1998-03-10

Mai, Tan V.

Boots, shoes, and leggings

364784, G06F 750

Patent

active

057269289

ABSTRACT:
An improved arithmetic logic operation circuit capable of advantageously reducing propagation delay due to a logic gate for obtaining a high speed arithmetic logic unit by minimizing the number of logic gates, which includes an even bit arithmetic logic unit cell for logically operating upon even bits of a first and second data and for generating a carry out signal in accordance with an inverted carry in signal, an inverted carry enable signal and an operation control signal, and an odd bit arithmetic logic unit cell for logically operating upon the odd bits of the first and second data and for generating a carry out signal in accordance with the carry in signal, a carry enable signal and the operation control signal.

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patent: 4931981 (1990-06-01), Knauer
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patent: 4989174 (1991-01-01), Gardei

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