Arithmetic logic unit and microprocessor capable of effectively

Details Arithmetic logic unit and microprocessor capable of effectively Arithmetic logic unit and microprocessor capable of effectively

1997-10-24

1999-12-21

Treat, William M.

Electrical computers and digital processing systems: processing

Architecture based instruction processing

712 36, 712 37, 712221, G06F 930

Patent

active

06006322&

ABSTRACT:
An arithmetic logic unit capable of executing an instruction belonging to a user-defined instruction area at the same clock frequency as a hard-wired logic includes a memory storing data at an arbitrary address and outputting the data stored in the address when an instruction code and an operand data are applied as an address. When an instruction decoder decoding part of the instruction code for setting the memory to read mode or write mode is provided, contents of the memory can be re-written, and therefore the content of the memory can be readily changed even after delivery. The arithmetic logic unit may include, in place of the memory, a programmable logic device adapted to receive an instruction code and the operand data and capable of organizing a desired logic.

REFERENCES:
patent: 5574942 (1996-11-01), Colwell et al.
patent: 5694360 (1997-12-01), Iizuka et al.
patent: 5748979 (1998-05-01), Trimberger
patent: 5752035 (1998-05-01), Trimberger
patent: 5829031 (1998-10-01), Lynch
Andre Detton, "Notes on Coupling Processors with Reconfigurable Logic," Transit Note #118, MIT Transit Project, Mar. 21, 1995.

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