Arithmetic logic unit

Details Arithmetic logic unit Arithmetic logic unit

1990-02-23

1992-01-14

Harkcom, Gary V.

Boots, shoes, and leggings

364749, G06F 750, G06F 738

Patent

active

050816071

ABSTRACT:
A digital arithmetic logic unit in which the carry chain is subdivided into a series of bit fields allowing independent and simultaneous data manipulation to be undertaken in each of the bit fields. Division of the carry chain is achieved via a carry chain selector consisting of a series of multiplexers, one being placed between each pair of adjacent stages of the carry chain. Each multiplexer has two data inputs, one of which forms the carry to the next stage of the carry chain. The carry selected either continues the computation or defines the end of one bit field and provides the least significant carry-in bit to the next bit field. This selection of the carry by the multiplexer is under control of a programmable register, thus allowing variable division of the carry chain.

REFERENCES:
patent: 3683163 (1972-08-01), Hanslip
patent: 4707800 (1987-11-01), Montrone et al.
patent: 4901270 (1990-02-01), Galbi et al.
patent: 4942549 (1990-07-01), Jutand et al.

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