Arithmetic logic unit

Details Arithmetic logic unit Arithmetic logic unit

1982-08-03

1985-09-17

Thomas, James D.

Boots, shoes, and leggings

G06F 738

Patent

active

045424764

ABSTRACT:
An arithmetic logic unit processes a variable operand length instruction such as a decimal arithmetic operation instruction, a plurality of bytes at a time using a multi-byte depth arithmetic operation unit. Multi-byte data including first and second operands are supplied to the arithmetic logic unit through a suppressing circuit. The suppressing circuit suppresses unnecessary bytes other than operand bytes and suppresses all of the bytes of one of the operands when the one operand has been exhausted.

REFERENCES:
patent: 3916388 (1975-10-01), Shimp et al.
patent: 4021655 (1977-05-01), Healy et al.
patent: 4023023 (1977-05-01), Bourrez et al.
patent: 4224682 (1980-09-01), Kindell et al.
patent: 4276596 (1981-06-01), Flynn et al.
patent: 4384340 (1983-05-01), Tague et al.

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