Arithmetic logic system using the output of a first alu to contr

Details Arithmetic logic system using the output of a first alu to contr Arithmetic logic system using the output of a first alu to contr

1985-10-07

1988-06-28

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 738

Patent

active

047544120

ABSTRACT:
An arithmetic logic system for performing a variety of arithmetic and logical functions on pixel input streams such as averaging down the input image stream, computation of absolute values, and signed or unsigned, clipped or unclipped, addition, subtraction and multiplication. The arithmetic logic system has a first arithmetic logic unit connected to a plurality of input signals. A second arithmetic logic unit is coupled to the first arithmetic logic unit and operates on the output of the first arithmetic logic unit. A control unit is coupled to the first and second arithmetic logic units and controls the operation of the second arithmetic logic unit based on the output of the first arithmetic logic unit.

REFERENCES:
patent: 3875391 (1975-04-01), Shapiro et al.
patent: 4242733 (1980-12-01), Deal
patent: 4377846 (1983-03-01), Yoshida
patent: 4407018 (1983-09-01), Kanemasa
patent: 4467444 (1984-08-01), Harmon, Jr. et al.
patent: 4653112 (1987-03-01), Ouimette

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