Arithmetic logic apparatus for a data processing system

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364768, G06F 750

Patent

active

042728282

ABSTRACT:
Arithmetic logic apparatus having two independent register files, one for each operand. Each register file has also associated therewith independently controlled incrementing and/or decrementing address mechanisms. Each such register file is coupled for addressing on a digit, byte or word basis. Operation of such apparatus is under the control of control instructions received from a control store included in a data processor in which such apparatus is also included.

REFERENCES:
patent: 3030019 (1962-04-01), Smith
patent: 3988717 (1976-10-01), Kisylia
patent: 4064554 (1977-12-01), Tubbs
patent: 4079451 (1978-03-01), Woods et al.
patent: 4085450 (1978-04-01), Tulpule

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