Arithmetic engine with dual multiplier accumulator devices

Details Arithmetic engine with dual multiplier accumulator devices Arithmetic engine with dual multiplier accumulator devices

1995-02-24

1996-05-28

Bowler, Alyssa H.

Boots, shoes, and leggings

364754, 364736, 3647365, 364768, G06F 752

Patent

active

055220851

ABSTRACT:
An arithmetic engine includes a first dual multiplier accumulator (MAC) for receiving input data and for producing first dual MAC output data. A second dual MAC is coupled in parallel to the first dual MAC. The second dual MAC receives the input data and produces second dual MAC output data. An adder array is coupled to both the first dual MAC and to the second dual MAC. The adder array receives the input data, the first dual MAC output data, and the second dual MAC output data and produces arithmetic engine output data. Each dual MAC comprises a multiplier cross point switch, multiplier registers, a register selector, and parallel multipliers. Each adder array comprises a cross point switch, adder registers, a register selector, adder, and condition code determiner.

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