Arithmetic device and method with low power consumption

Details Arithmetic device and method with low power consumption Arithmetic device and method with low power consumption

1999-12-01

2003-09-30

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06629119

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to an arithmetic device with low-power consumption and method of reducing power consumption of an arithmetic device. The principle of design is to detect the effective dynamic range of the input data before performance of operations, and then perform the operations of the bits of the dynamic range so as to reduce the switching frequency of the switch of said arithmetic device and thereby reduce the power consumption.
BACKGROUND OF THE INVENTION
Reducing power consumption is a current design factor of microprocessors and communication products. Such products often use devices, which in many applications, particularly for multimedia generally consume power by the charge-discharge operations at the capacitance nodes. The power consumed is:
P
switching
=&agr;CV
dd
2
f
clk
  (1)
where &agr; is the switching activity, C is the load capacitance, V
dd
is the operating voltage, and f
clk
is the operating frequency. Further, &agr;C is considered to be the effective load capacitance for charge-discharge activities.
It can be seen from equation (1) that power consumption can be minimized by: reducing the operating voltage, reducing the operating frequency, and reducing the effective load capacitance. Since the reduction of operating voltage and operating frequency also results in a reduction of the performance of the circuit, the reduction of load capacitance is the best alternative for reducing power consumption without affecting performance.
Generally, reducing the effective load capacitance can be accomplished with an algorithm for improving the operating modes (reducing charge-discharge frequency) or the circuit construction. Taking a fixed-point number system for example (whether represented in 1 or 2 complement), when the change of positive and negative numbers is processed, the load capacitance continues to charge or discharge due to sign extension, thus resulting in excessive power consumption. Therefore, the sign-magnitude number system has been proposed for data interpretation. As a result, the sign-extension bits of the positive and negative numbers are substituted with a bit to save the power consumption of the sign-extension bits when the effective dynamic range of the input data do not span the entire word length. However, this method complicates the circuit construction.
SUMMARY OF THE INVENTION
Accordingly, a primary object of this invention is to provide an arithmetic device and method for reducing power consumption without reducing the operating voltage or the operating frequency of circuitry in the device.
Another object of this invention is to provide an arithmetic device and method for reducing power consumption, which determines the particular functional blocks of an arithmetic device that will be used according to the effective dynamic range of input data. Consequently, power consumption of unused functional blocks of an arithmetic device can be prevented.
A further object of this invention is to provide an arithmetic device and method for reducing power consumption, wherein low-power operations are realized with data types of a digital system.
Yet another object of this invention is to provide an arithmetic device and method with reduced power consumption for various operating units which meet the mainstream needs for portable products as well as environmental protection.
To achieve the above and other objects, this invention provides a low power consumption arithmetic device comprising master latches, a dynamic range detection unit, slave latches, an operation unit, and a word-length restoration unit. In said arithmetic device, the master latches latch plural (such as two) input data. The dynamic range detection unit detects the effective dynamic range of these input data. The slave latches store the values of effective dynamic-range bits of these input data. The operation unit performs predetermined operations of the effective dynamic-range bits for obtaining an operation result. Since the operation unit performs only operations of the effective dynamic-range bits, the circuit corresponding to the other bits will not demonstrate switching (power consumption), thereby lowering the overall power consumption. Furthermore, the word-length restoration unit will compensate the operation result to its original output length in association with the sign of the operation result, for obtaining the correct operation result.
In said arithmetic device with low power consumption, the master latches and the slave latches are formed with flip-flops. Moreover, the operation unit can be an adder, a multiplier or another device.
Further, this invention also provides a method of reducing the power consumption of the arithmetic device in the following basic steps: first, input plural operating data and detect the dynamic ranges of said plural data; next, perform predetermined operations of the effective dynamic-range bits of input data A and B to obtain an operation result. Then, compensate the output data to the original output length in accordance with the effective dynamic range and the sign of the operation result. Consequently, the correct operation result is realized with less switching (less power consumption).


REFERENCES:
patent: 5390135 (1995-02-01), Lee et al.
patent: 5404474 (1995-04-01), Crook et al.
patent: 5517439 (1996-05-01), Suzuki et al.
patent: 5615140 (1997-03-01), Ishikawa
Chandrakasan et al., “Minimizing Power Consumption in Digital CMOS Circuits”, Proceedings of the IEEE, vol. 83, No. 4, pp. 498-523, Apr. 1995.
Tong et al., “Minimizing floating-point power dissipation via bit-width reduction” pp. 114-118, Proc. of Power Driven Microarchitecture Workshop, Spain, Jun., 1988.
Phatak, D., “Hybrid Signed Digit Representation for Low Power Arithmetic Circuits”, pp. 124-129, Proc. of Power Driven Microarchitecture Workshop, Spain, Jun., 1988.

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