Arithmetic circuits for digital filters

Details Arithmetic circuits for digital filters Arithmetic circuits for digital filters

1981-08-06

1984-02-07

Malzahn, David H.

Boots, shoes, and leggings

G06F 1531

Patent

active

044307217

ABSTRACT:
A digital filter is provided which selectively employs binary arithmetic and offset two's complement arithmetic in an adder ladder to protect against signal overflows and underflows, as well as to minimize adder size. Signal overflows and underflows are prevented by performing subtraction and certain additions in offset two's complement notation, while adder sizes are minimized by performing certain other additions in binary notation. In an alternate embodiment, positively weighted values are combined by binary addition in a first adder ladder, and negatively weighted values are combined by binary addition in a second, parallel adder ladder. At the outputs of the two ladders, the two sums are converted to offset two's complement notation, and the negatively weighted sum is subtracted from the positively weighted sum.

REFERENCES:
patent: 3696235 (1972-10-01), Tufts et al.
patent: 3725687 (1973-04-01), Heightley
patent: 3949206 (1976-04-01), Edwards et al.
patent: 4104729 (1978-08-01), Gingell
Article, "Special-Purpose Hardware for Digital Filtering", by Stanley L. Freeny, Proc. IEEE, vol. 63, pp. 633-648, (Apr. 1975), pp. 63-64.
Article "Two's Complement Pipeline Multipliers", by R. F. Lyon, IEEE, Trans. Commun., vol. COM-24, pp. 418-425, (Apr. 1976), p. 240.
The Advanced Micro Devices Databook on "Schottky and Low-Power Schottky, Bipolar Memory, Logic and Interface", 1975, (beginning on p. 5-19).
Tubiana, "Digital Filter Having Integral Coefficients", IBM Tech. Disc. Bulletin, vol. 18, No. 10, Mar. 1976, pp. 3322-3324.
Moon et al., "A Digital Filter Structure Requiring Only m-Bit Delays, Shifters, Inverters, and m-Bit Adders Plus Simple Logic Circuitry", IEEE Trans. on Circuits and Systems, vol. CAS-27, No. 10, Oct. 1980, pp. 901-908.

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