Arithmetic circuit with balanced logic levels for low-power...

Details Arithmetic circuit with balanced logic levels for low-power... Arithmetic circuit with balanced logic levels for low-power...

2005-03-03

2008-03-25

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07349938

ABSTRACT:
An adder circuit includes a plurality of adder stages interconnected in series, with a carry out of each of the adder stages other than a final adder stage being coupled to a carry in of a subsequent one of the adder stages. Carry, generate and propagate signals applied to respective inputs of a carry out computation element in at least a given one of the adder stages are substantially balanced in terms of a number of gate delays experienced by the signals within the adder circuit in arriving at their respective inputs of the carry out computation element. Advantageously, this provides significant reductions in both dynamic switching power and short circuit power in the adder circuit.

REFERENCES:
patent: 3925652 (1975-12-01), Miller
patent: 5278783 (1994-01-01), Edmondson
patent: 5477480 (1995-12-01), Inui
patent: 5745397 (1998-04-01), Nadehara
patent: 6301600 (2001-10-01), Petro et al.
patent: 2002/0188640 (2002-12-01), Catherwood
patent: 2003/0115237 (2003-06-01), Fletcher
patent: 2003/0120901 (2003-06-01), Hokenek et al.
patent: 2005/0060359 (2005-03-01), Schulte et al.
patent: 2005/010746 (2005-02-01), None

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