Arithmetic circuit for accumulative operation

Details Arithmetic circuit for accumulative operation Arithmetic circuit for accumulative operation

1999-05-10

2003-02-11

Ngo, Chuong Dinh (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S709000

Reexamination Certificate

active

06519621

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to an improved arithmetic circuit for accumulative operation for use in digital signal processors, microprocessors and so forth, in which the pipelined control becomes effective during accumulative operation by eliminating idling stage in the pipeline.
2. Prior Art
In the accumulative operation for repeatedly performing a series of processing steps in a microprocessor with one cycle of operation being conducted by making use of the result of the previous cycle of operation, the overall processing speed is largely affected by the processing time required for the propagation of carries. For this reason, in the prior art technique, the processing speed for handling carries is conducted by making use of a CSA (Carry Save Adder) in advance of a CPA (Carry Propagation Adder), e.g., in the case that the operands are input with carries. The CSA is composed of a series of FAs (full adders) for high speed addition operation of three operands. One of the three operands is input to the carry-input terminals as carry-in signals while the resultant carry-out signals is output to the next stage rather than input to the adjacent FAs respectively. The final result can be obtained by 2-input adder, i.e., the CSA, provided for adding the outputs of the CSA.
On the other hand, the timing alignment between the two adders, i.e., the CPA and the CSA is established by making use of appropriate data latching circuits therebetween. The data latching circuits are required, for example, in the case that the operation time required in the CPA is relatively long as compared with the machine cycle time or in the case that the CPA is a circuit which operates under a certain timing restriction such as a precharge-type circuit.
In the following explanation, the operation of prior art arithmetic circuits provided with such data latching circuits will be explained with reference to the accumulative addition and the accumulative subtraction.
First of all, the prior art accumulative addition will be explained with reference to FIG.
1
. As illustrated in
FIG. 1
, two input data operands Ai and Bi and the data latched on to an output register 32 are added, and the result is written to the output register 22. The result of the addition Ai+Bi is accumulated by repeating this process. Namely, the operation is performed as in the following equation.
(Initial Data)+(A
0
+B
0
)+(A
1
+B
1
)+ . . .
The two input data operands are given with a variety of applications. In one typical case, one input data A is comprised of carries while the other input data B is comprised of sums in a carry saved fashion for accumulative addition.
The accumulative adder comprises a selector circuit (multiplexer)
31
for selecting data to be loaded from arbitrary data and the outputs of the adder, an output register
32
for storing the outputs of the selector circuit
31
, a CSA
33
for receiving the outputs of the output register
32
and input data operands Ai and Bi, intermediate result latching registers
34
and
35
for latching the outputs of the CSA
33
and a CPA
36
for receiving the outputs of the registers
34
and
35
as illustrated in FIG.
1
.
Next, the arithmetic operation of the accumulative adder will be explained in the followings.
(Machine Cycle
1
)
First of all, initial data is selected by the selector circuit
31
and written to the register
32
in order to load the initial data for addition.
(Machine Cycle
2
)
In the next cycle, the CSA
33
performs the addition of the input data operands Ai and Bi and the outputs of the register
32
as input signals. The result of the addition is output as carries S
1
and the sums S
2
and latched on to the intermediate result latching register
34
respectively.
(Machine Cycle
3
)
Next, the CPA
36
performs the addition of data as latched on to the register
34
and the register
35
. The result of the addition as calculated by the CPA
36
is selected and written to the output register
32
.
The addition operation is repeated by repeating the machine cycles
2
and
3
.
Next, the prior art arithmetic circuit for accumulative subtraction will be explained with reference to FIG.
2
.
The accumulative subtraction is performed by the subtraction formula.
(Initial Data)−(Input A
0
+Input B
0
)−(Input A
1
+Input B
1
) . . .
Also in this case, the operands are input in the form of carries and sums in which, for example, one input data operand Ai stands for carries while the other data operand Bi stands for sums in a carry saved fashion for accumulative subtraction, in the same manner as the addition circuit as described above. From the subtraction formula, the accumulative subtraction is represented by the following equation with input data Ai and Bi as a subtrahend and the initial data or the result of the previous accumulative subtraction as a minuend.
P1
-
(
A
0
+
B
0
)
=
P1
_
+
A
0
+
B
0
_
Accordingly, the accumulative subtraction is realized by combination of an inverter and an adder.
The accumulative subtraction circuit is composed of a selector circuit
31
for selecting and outputting either of data to be loaded to the register
32
(the initial data) or the outputs of the adder, a register
32
for latching the outputs of the selector circuit
31
, an inverter
37
for inverting the outputs of the register
32
, a CSA
33
for receiving the outputs of the output register
32
and input data operands Ai and Bi, intermediate result latching register
34
and
35
for latching the carry and sums of the CSA
33
, a CPA
36
for receiving the outputs of the registers
34
and
35
and an inverter
38
for inverting the outputs of the CPA as illustrated in FIG.
2
.
Next, the arithmetic operation of the accumulative subtracter will be explained in the followings.
(Machine Cycle
1
)
First of all, initial data is selected by the selector circuit
31
and written to the register
32
in order to load the initial data for addition.
(Machine Cycle
2
)
In the next cycle, the CSA
33
performs the addition of the input data A and B and the inversion of the outputs of the register
32
as input signals in accordance with the following equation.
({overscore (P
1
)}+A
0
+B
0
)
The result of the addition is output as carries S
1
and the sums S
2
and latched on to the intermediate result latching register
34
and
35
.
(Machine Cycle
3
)
Next, the CPA
36
performs the addition of data as latched on to the register
34
and the register
35
. The result of the addition as performed by the CPA
36
is inverted and outputted through the inverter
38
. In this cycle, the selector circuit
31
selects the inversion of the output result of the CPA
36
, followed by writing the operation result in accordance with the following equation to the register
32
.
(
P1
_
+
A
0
+
B
0
_
)
The subtraction operation is repeated by repeating the machine cycles
2
and
3
, and after completing predetermined times of the repetition, the final result of the accumulative subtraction is obtained in the output register
32
.
However, there are following shortcomings in the prior art accumulative arithmetic circuits as described above. These shortcomings will be explained with reference to FIG.
3
. Namely, in the field to which the present invention pertains, pipelined control is usually implemented for the purpose of improving the processing speed of the operation. In the pipelined control, each instruction is divided into a plurality of the processing stages so that a plurality of instructions can be executed in parallel in different stages.
Namely, execution of one instruction can be initiated while the previous instruction is being executed.
However, the repetition of the prior art accumulative operation is possible only by reading and referring to the previous operation result. Namely, as illustrated in
FIG.3
which shows a series of the accumulative addition operation (instruction
1
, instruction
2
, instruction
3
and so forth), each operation

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