Arithmetic circuit, and adaptive filter and echo canceler using

Details Arithmetic circuit, and adaptive filter and echo canceler using Arithmetic circuit, and adaptive filter and echo canceler using

1992-02-28

1994-03-22

Nguyen, Long T.

Boots, shoes, and leggings

G06F 700

Patent

active

052970710

ABSTRACT:
In the digital signal processor used for realizing application filters, the filter output calculation processing system 5 and the tap coefficient update calculation processing system 6 are separated. In the update calculation processing system 6, the integrating calculation for the tap coefficient updating that requires read and write operations on the data memory DRM is performed in one machine cycle by using the dedicated data bus 10 and executing the read-modify-write operation on the data memory. As a result, to the extent that the time taken by the integrating processing which has conventionally required two machine cycles can be shortened, the operation clock frequency can be lowered to reduce the power consumption while maintaining the processing capability per unit of time.

REFERENCES:
patent: 4736288 (1988-04-01), Shintani et al.
patent: 4785393 (1988-11-01), Chu et al.
patent: 4942547 (1990-07-01), Joyce et al.
patent: 5142489 (1992-08-01), Yamaki
K. Kloker, "The Motorola DSP56000 Digital Signal Processor", IEEE Micro, Dec. 1986, pp. 29-48.
TMS320C25 User's Manual, Texas Instruments Japan, Ltd., p. 3-2-3-6, 1989.

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