Arithmetic circuit

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Reexamination Certificate

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10692690

ABSTRACT:
There is provided an arithmetic circuit for minimizing the delay of data path from the input of data to be operated to the output of the result of operation of data. To that end, the arithmetic circuit comprises a first selector to which one input data and a fixed data are inputted wherein these data are selectively outputted in response to a control signal, a second selector to which another input data and an output data of a register are inputted wherein these data are selectively outputted in response to the control signal, an adder for receiving an output signal of the first selector and an output signal of the second selector to execute the addition of the output signals of the first and second selectors, and a register for receiving an output signal of the adder to hold the output signal in synchronization with a clock signal.

REFERENCES:
patent: 5329477 (1994-07-01), Kudou
patent: 5375079 (1994-12-01), Uramoto et al.
patent: 5511017 (1996-04-01), Cohen et al.
patent: 6263424 (2001-07-01), Tran et al.
patent: 6480874 (2002-11-01), Aidan et al.
patent: 6925480 (2005-08-01), Duborgel
patent: 6989843 (2006-01-01), Naegle et al.
patent: 05-80978 (1993-04-01), None
patent: 2002-132492 (2002-05-01), None

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