Arithmetic apparatus for use in Viterbi decoding

Details Arithmetic apparatus for use in Viterbi decoding Arithmetic apparatus for use in Viterbi decoding

1997-10-14

1999-10-19

Le, Amanda T.

Pulse or digital communications

Systems using alternating or pulsating current

Plural channels for transmission of a single pulse train

375341, 714795, 714796, H03M 1312

Patent

active

059700971

ABSTRACT:
An arithmetic apparatus comprising a memory 1 for storing path select signals, a barrel shifter 3 for shifting data read from the memory, a shift register 4 for receiving a bit shifted to a MSB by the barrel shifter and means 5 for generating the number of shifts which are performed by the barrel shifter by converting data positioned at a specific bit position in the shift register, wherein path select signals at the same time are divided into a plurality of groups, and then stored in the memory, and the arithmetic apparatus includes address generating means 10 for outputting the address, and address conversion means 7 for generating the address of the group which must be read by combining the address and a value of a specific bit position in the shift register with each other. Thus, tracing back in Viterbi decoding can be performed with a short bit width.

REFERENCES:
patent: 5802115 (1998-09-01), Meyer

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