Arithmetic apparatus for floating-point numbers

Details Arithmetic apparatus for floating-point numbers Arithmetic apparatus for floating-point numbers

1995-06-05

1997-10-14

Mai, Tan V.

Boots, shoes, and leggings

G06F 738

Patent

active

056778619

ABSTRACT:
In the case of addition/subtraction of floating-point numbers, two mantissas having their digits aligned in a swapper and in a right shifter are supplied to an adder/subtracter via first and second mantissa selectors and two 1-bit right shifters so that they are subjected to addition/subtraction in the adder/subtracter, the result of which is rounded. In the case of multiplication/division of floating-point numbers, an intermediate sum and a carry, each outputted from a multiplier, are supplied to the above adder/subtracter via the above first and second mantissa selectors and the above two 1-bit right shifters, so that they are added in the adder/subtracter, the result of which is rounded. The result of rounding from the adder/subtracter is outputted as a normalized mantissa through a priority encoder and a left shifter. An exponent is processed by first to third exponent arithmetic units and an exponent selector. Thus, the amount of hardware of an arithmetic apparatus for executing the addition, subtraction, multiplication, and division of floating-point numbers can be reduced.

REFERENCES:
patent: 4866652 (1989-09-01), Chu et al.
patent: 5204828 (1993-04-01), Kohn

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