Arithmetic and logic unit with overflow indicator

Details Arithmetic and logic unit with overflow indicator Arithmetic and logic unit with overflow indicator

1985-01-31

1987-11-10

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

047062096

ABSTRACT:
The invention concerns the overflow test circuit of an arithmetic and logic unit. The circuit described does not require receiving an indication on the operating in addition or subtraction of the ALU; it receives simply the carrying input the carrying and the result output of the cell of the highest rank of the ALU: and it supplies a positive overflow signal or a negative overflow signal, when the result of the addition or subtraction of two numbers exceeds the capacity of the ALU. Two gates with three inputs and three inverters are sufficient to establish the overflow test circuit.

REFERENCES:
patent: 4215415 (1980-07-01), Kanemasa et al.
patent: 4592008 (1986-05-01), Nopper
Nguyen, "Practical Hardware Solutions for 2's Complement Arithmetic Problems" Computer Design Jul., 1979, pp. 105-112.
IBM Technical Disclosure Bulletin, vol. 19, No. 8, Jan. 1977, New York (U.S), East et al. "Overflow Indication in Two's Complement Arithmetic" pp. 3135-3136.

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