Arithmetic and logic operating unit

Details Arithmetic and logic operating unit Arithmetic and logic operating unit

1987-02-09

1989-03-07

Harkcom, Gary V.

Communications: electrical

Digital comparator systems

364769, G06F 702

Patent

active

048109959

ABSTRACT:
An arithmetic and logic unit control circuit includes arithmetic circuits (10a-10d) for generating the absolute value .vertline.A.vertline. of an input signal A and the complement B of an input signal B from n-bit input signals A and B in response to a control signal from a controller (14). Full adders (6a-6d) add outputs from the arithmetic circuits in response to a control signal from the controller (14). First logic circuits (20a-20c, 21) extract the most significant bit of (.vertline.A.vertline.-B) to form outputs of the full adders (6a-6d) in response to a control signal from controller (14) and second logic circuits (20e, 21) to perform a three-level decision of values A and B from the outputs of the first logic circuits (20a-20c, 21) and the most significant bit of the input signal A. The arithmetic and logic unit can thereby perform Alternate Mark Inversion (AMI) coding in one machine cycle.

REFERENCES:
patent: 3434109 (1969-03-01), Coote
patent: 3955177 (1976-05-01), Miller
Ho et al., "Comparator Compare 2's Complement Number", Electronics, Aug. 25, 1983, pp. 138-139.
Mano, "Digital Logic and Computer Design", Chapter 9, Published by Prentice Hall, Inc. 1979.

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