Arithmetic and logic circuit stage

Details Arithmetic and logic circuit stage Arithmetic and logic circuit stage

1987-03-26

1989-02-14

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 750

Patent

active

048051306

ABSTRACT:
A circuit for performing operations on two bits (A,B), including the processing of a carry from a preceding circuit (CIN) and transmitting it to a subsequent circuit (COUT). The circuit includes a network which is formed by MOS transistors which can be programmed via programming lines and which supplies a logic combination. An exclusive carry-propagation-generation device is formed by three MOS transistors which are connected in series between a carry-propagation line and ground and whose gates are connected to one of the bits to be processed, to the logic combination, and to a carry inhibit line, respectively.

REFERENCES:
patent: 4563751 (1986-01-01), Barker
patent: 4621338 (1986-11-01), Uhlenhoff
Ong et al, "A Comparison of ALV Structures for VLSI Technology", 6th Symposium on Computer Arithmetics, Jun. 20-22, 1983 in Aarhus (DK), published by IEEE Computer Society.

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