Area pattern processing of pixels

Details Area pattern processing of pixels Area pattern processing of pixels

2005-08-02

2005-08-02

Chauhan, Ulka J. (Department: 2676)

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

C345S503000, C345S531000, C345S533000, C345S564000, C345S613000, C345S614000

Reexamination Certificate

active

06924808

ABSTRACT:
A circuit for outputting area pattern bits from an area pattern array. The circuit includes a first stage, second stage and third stage. The first stage is configured to output N adjacent scan lines from a 2N×2N area pattern array based on a first address. N is a positive integer. The second stage is configured to receive the N adjacent scanlines and to select an N×N block from the N adjacent scanlines based on a second address. The third stage is configured to (a) select an (N/2)×N region of bits from the N×N block and load bits of the (N/2)×N region into a set of pixel tag outputs in a first mode, and (b) select an N×(N/2) region of bits from the N×N block and load bits of the N×(N/2) region into the set of pixel tag outputs in a second mode.

REFERENCES:
patent: 5943060 (1999-08-01), Cosman et al.
patent: 6159152 (2000-12-01), Sumanaweera et al.

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