Electrical pulse counters – pulse dividers – or shift registers: c – Shift register – Compensating for or preventing signal deterioration
Reexamination Certificate
2001-11-13
2002-12-31
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Shift register
Compensating for or preventing signal deterioration
C377S026000, C377S054000, C377S075000, C365S200000, C365S201000, C714S718000, C714S805000
Reexamination Certificate
active
06501817
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit (“IC”) devices. More particularly, the present invention relates to an improved, integrated circuit area efficient, redundancy multiplexer circuit technique providing significantly reduced parasitic capacitance of particular applicability for use in integrated circuit memory devices and other semiconductor devices incorporating embedded memory elements.
Current integrated circuit memory redundancy technology often utilizes numbers of conventional, complementary metal oxide semiconductor (“CMOS”) transmission, or “pass” gates for each repairable element, with each such pass gate comprising parallel coupled N-channel and P-channel transistors controlled by complementary gate control signals. Functionally, these pass gates are often utilized for shifting addresses as well as the read/write data of redundant circuit elements.
For example, the address path of regular as well as spare row and column elements (and the data flow of a data path) can be directed through the use of pass gate logic. In the conventional CMOS implementation of a pass gate, the input signals can be propagated without a threshold voltage (“V
t
”) drop in the signal level as would be the case if only a single N-channel or P-channel transistor were used instead. In the former instance, the N-channel device would introduce a V
t
drop to logic “one” signal levels and in the latter case, the P-channel device would introduce a V
t
drop to logic “zero” signal levels.
Although CMOS pass gates designs are traditionally well suited for these purposes, the layout of such circuits nevertheless consumes an undesirably large amount of integrated circuit die (“on-chip”) area and adds concomitant circuit complexity with the need for complementary control signal generation, routing and other attendant requirements. This additional die space and layout complexity adds to an increased device cost and design time while also exhibiting a significantly large parasitic capacitance, leading to a decrease in the speed of the address and data paths. Further, while single device pass gates circuit techniques have been utilized before, their use has generally been limited to those applications wherein the voltage drop across the conducting transistor is either not critical or can be thereafter boosted through a subsequent amplification stage. Moreover, single device pass gates have not heretofore been utilized in conjunction with shift redundancy techniques.
SUMMARY OF THE INVENTION
The improved integrated circuit area efficient redundancy multiplexer circuit technique of the present invention disclosed herein advantageously provides similar functionality to conventional CMOS transmission, or “pass” gates while concomitantly reducing circuit complexity, the die area necessary to support redundant elements in memory device ICs and providing much reduced parasitic capacitance. The technique of the present invention effectuates this end by utilizing the on-chip boosted voltage levels (V
pp
) which are generally available in such devices while the significant reduction provided in undesired parasitic capacitance enables higher throughput speeds in the address and data paths.
In a particular embodiment of the present invention disclosed herein, a single N-channel pass transistor uses the V
pp
voltage level (which is boosted above the normal supply voltage level of V
cc
) to supply the voltage for the control signal applied to the N-channel transistor gate. The voltage level V
pp
and circuit ground (“GND”) are then utilized as the logic “high” and “low” signal levels respectively. This use is made possible due to the fact that these control signals operate at a direct current (“DC”) level after device power-up. When the integrated circuit device has come up and is stabilized (and after the redundancy has been programmed), then the signal levels of the N-channel pass gates are stabilized.
Particularly disclosed herein is an integrated circuit device having a supply voltage level applied thereto relative to a reference voltage level and a boosted voltage level greater than the supply voltage level. The device includes a redundancy multiplexer circuit which comprises a plurality of switching devices, with each of the switching devices coupled between a respective input signal line and a common output signal line. A plurality of control signal lines are also provided, with each of the control signal lines coupled to a control terminal of a corresponding one of the switching devices. The switching devices are operative in response to a control signal applied to the control terminal thereof at the boosted voltage level for passing an input signal on a corresponding input signal line to the output signal line without a threshold voltage drop thereacross.
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patent: 5818258 (1998-10-01), Choi
patent: 5825235 (1998-10-01), Oh
patent: 5909141 (1999-06-01), Tomishima
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Hardee Kim
Parris Michael
Hogan & Hartson LLP
Kubida William J.
Meza Peter J.
United Memories Inc.
Wambach Margaret R.
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