Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2006-02-28
2006-02-28
Chaki, Kakali (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
07007053
ABSTRACT:
An area-efficient realization of a coefficient block includes hardware sharing techniques and optimizations applied to this block. The block is connected to coefficient lines coming from a delay block to be connected to perform a filtering operation or a mathematical computing operation with optimization in hardware and provides a zero latency output. The coefficient block also enables an area minimal realization of digital filters based on the coefficient block, when operated in serial bit fashion. The optimization techniques and structure are good for bit-serial digital filters typically a finite impulse response (FIR) filter, including finite impulse response filter (IIR) and for other filters and applications based on combinational logic that includes delay elements, multipliers, and serial adders and/or subtractors.
REFERENCES:
patent: 4752905 (1988-06-01), Nakagawa et al.
patent: 4982354 (1991-01-01), Takeuchi et al.
patent: 5262972 (1993-11-01), Holden et al.
patent: 5497342 (1996-03-01), Mou et al.
patent: 5692020 (1997-11-01), Robbins
patent: 6370556 (2002-04-01), Saramaki et al.
patent: WO 94/23493 (1994-10-01), None
Dawood Alam et al, “VLSI Implementation of a New Bit-Level Pipelined Architecture for 2-D Allpass Digital Filters,”Institute of Electrical and Electronics Engineers, 1: 724-727, Apr. 30-May 3, 1995.
K. Manivannan et al., “Minimal Multiplier Realization of 2-D All-Pass Digital Filters”,IEEE Transactions on Circuits and Systems, 35(4):480-484, Apr. 1998.
Goel Puneet
Malik Rakesh
Chaki Kakali
Do Chat C.
STMicroelectronics Asia Pacific (Pte) Ltd.
LandOfFree
Area efficient realization of coefficient architecture for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Area efficient realization of coefficient architecture for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Area efficient realization of coefficient architecture for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3679013