Area efficient programmable frequency divider

Details Area efficient programmable frequency divider Area efficient programmable frequency divider

2007-12-04

2007-12-04

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S117000

Reexamination Certificate

active

11213436

ABSTRACT:
A programmable high-speed frequency divider is provided in which a stage for forming a frequency divider, which is capable of being programmed with a programmable dividing ratio, is simplified in order to reduce the area and circuit complexity. The programmable frequency divider includes a first synchronizing element coupled to an output of a logic detection circuit for generating a synchronized divider output, an additional synchronizing element coupled to the output of the logic detection circuit for receiving its clock from the output of a divide-by-two circuit and generating a special synchronized load output, and combinational logic blocks that receive the load output and generate load signals for bit-cells for detecting the state of all stages. Preferably, start-up circuitry is included within the frequency divider to ensure that the frequency-divider never goes into a false state.

REFERENCES:
patent: 6882189 (2005-04-01), Tam et al.
patent: 2003/0071664 (2003-04-01), Magen
patent: 2004/0222825 (2004-11-01), De Gouy et al.
Larsson, Patrik: “High-Speed Architecture for a Programmable Frequency Divider and a Dual-Modulus Prescalar,” May 1996, IEEE Journal of Solid-State Circuits, vol. 31, No. 5, pp. 744-748.

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