Area efficient, low power and flexible time digitizer

Details Area efficient, low power and flexible time digitizer Area efficient, low power and flexible time digitizer

2002-11-12

2004-04-13

Pascal, Robert (Department: 2817)

Computer graphics processing and selective visual display system

Display driving control circuitry

Display power source

C331S057000

Reexamination Certificate

active

06720959

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to any system that requires obtaining a digital measurement of the duration of a pulse over a large range of pulse widths that can span orders of magnitude. The range is determined by the ratio of longest pulse width to the shortest one to be measured. More particularly, this invention applies to a non-linear time digitizer delay chain and a respective lookup table for converting a pulse with a specific time duration into a digital code. The error in measuring the time duration of the pulse width in this invention is bounded to be below a fixed percentage of the pulse duration. Measurements of the duration of a pulse width, such as phase error, are typically needed in common systems such as digital phase or delay locked loops.
2. Description of the Prior Art
Digital time measurement has been commonly used in digital phase locked loop implementations. Many designers have chosen a complete digital phase lock loop (DPLL) approach to address requirements such as wide range of input clock frequency, low power supply voltage, wide processing and temperature variations versus an alternative traditional analog implementation of the phase locked loop (APLL). Such digital phase lock loops (DPLLs) are running entirely in the digital domain except for the digitally-controlled oscillator (DCO). Traditionally, some sort of time digitizer (T2D) circuit is employed to convert the phase error into a digital code. This is problematic however, as the input frequency can sometimes vary by orders of magnitude, where the design of the T2D delay chain becomes more challenging as more and more delay buffers are added to cover longer range of pulse durations in order to prevent the phase error pulse from saturating the delay chain. This linear growth with pulse duration will require a linear increase in the number of buffers used and hence increases both silicon area as well as power consumption.
It is therefore advantageous and desirable to provide a technique of implementing a time digitizer delay chain for converting the phase error associated with a digital PLL into a digital code in a way that prevents a phase error pulse from saturating the delay chain, even when the input frequency varies by orders of magnitude. It would be further advantageous and desirable if the time digitizer delay chain were to be implemented in a fashion to minimize required silicon area as well power consumption.
SUMMARY OF THE INVENTION
The present invention is directed to a non-linear time digitizer delay chain and a respective lookup table for converting a pulse width into a digital code, and that together prevent a pulse from saturating the delay chain, even when the pulse duration varies by orders of magnitude. By using a non-linear T2D delay chain along with a corresponding lookup table, the pulse width can be measured and represented in more meaningful and accurate ways to that achievable when using a conventional T2D circuit to convert the pulse width into a digital code. The total delay chain can be partitioned into small piece-wise linear delay segments while keeping the total number of digital codes required to a minimum. Without increasing the complexity of interface routing between the T2D and its associated digital controller, the digital code is converted through a lookup table to recover the actual pulse duration information. More importantly, the lookup table implementation allows an additional degree of freedom for designers to apply a transfer function to the digital code measured by the T2D. For example, such a function can behave as a pre-emphasis filter that will improve or compensate for the loop gain or correct for circuit non-linearity.
According to one embodiment, a time digitizer system comprises a delay chain configured to generate a different code corresponding to monotonically increasing (for example exponenetial) pulse durations. Corresponding to each of these digital codes a digital value is entered in a look-up-table. Hence, for a range of pulse durations, there is a unique code generated from the combined look-up-table and delay chain. This combined operation can generate any time to digital transfer function to achieve desired mapping of pulse duration and corresponding digital code.
One embodiment of this invention is by using a mapping of exponentially increasing pulse width durations to an intermediate digital code, which is logarithmically related to the pulse width duration. After the look-up-table, this intermediate code is transformed to an output code that is linearly related to the original pulse duration. The advantage of using this logarithmic compression and further exponential expansion of codes is that the size and power required for the implementation can grow only logarithmically with the range of pulse duration while maintaining a measurement resolution that is bounded to be below a fixed percentage of the pulse duration.
According to yet another embodiment, a time digitizer system comprises a delay chain having a first transfer function and configured to generate a intermediate digital code in response a pulse duration; and a look-up table comprising data associated with a second transfer function, such that the intermediate digital code is modified by the second transfer function data to provide a final digital code.


REFERENCES:
patent: 4677648 (1987-06-01), Zurfluh
patent: 5444459 (1995-08-01), Moriyasu
patent: 6628276 (2003-09-01), Elliott

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