Area efficient 3D integration of low noise JFET and MOS in...

Details Area efficient 3D integration of low noise JFET and MOS in... Area efficient 3D integration of low noise JFET and MOS in...

2011-05-10

2011-05-10

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C257S350000, C257SE27112, C257SE29262, C257SE21561, C257SE21614, C438S155000, C438S156000, C438S186000

Reexamination Certificate

active

07939863

ABSTRACT:
Analog ICs frequently include circuits which operate over a wide current range. At low currents, low noise is important, while IC space efficiency is important at high currents. A vertically integrated transistor made of a JFET in parallel with an MOS transistor, sharing source and drain diffused regions, and with independent gate control, is disclosed. N-channel and p-channel versions may be integrated into common analog IC flows with no extra process steps, on either monolithic substrates or SOI wafers. pinchoff voltage in the JFET is controlled by photolithographically defined spacing of the gate well regions, and hence exhibits low variability.

REFERENCES:
patent: 6153453 (2000-11-01), Jimenez
patent: 6784470 (2004-08-01), Davis
patent: 7642617 (2010-01-01), Chen et al.

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