Architectures, circuits, systems and methods for reducing...

Details Architectures, circuits, systems and methods for reducing... Architectures, circuits, systems and methods for reducing...

2003-08-04

2009-02-03

Wang, Ted (Department: 2611)

Pulse or digital communications

Repeaters

Including pulse regeneration or conversion

C375S327000, C375S373000, C375S376000, C455S180300

Reexamination Certificate

active

07486718

ABSTRACT:
Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circuit receiving recovered clock signal information and providing a control signal that adjusts the transmitter clock in response to recovered clock signal information and the two clock signals, and a transmitter receiving the control signal and transmitting data to a destination device in accordance with the transmitter clock. The circuitry generally includes a clock alignment block receiving first and second periodic signals and providing a control signal in response thereto, a filter for first periodic signal information, and a logic circuit configured to combine the control signal and the filtered information, thereby providing an adjustment signal for the second periodic signal. The systems generally relate to those that include the present architecture and/or circuit. The method generally includes determining a phase difference between first and second periodic signals, one of the periodic signals being recovered from a data stream; adjusting the other periodic signal in response to the phase difference and filtered information from the recovered periodic signal; and transmitting the data stream in accordance with said adjusted periodic signal. The present invention advantageously eliminates a FIFO memory in the data path, thereby reducing transceiver latency and improving system performance.

REFERENCES:
patent: 6513085 (2003-01-01), Gugel et al.
patent: 6982974 (2006-01-01), Saleh et al.
patent: 7050777 (2006-05-01), Cai
patent: 7088976 (2006-08-01), Gregorius et al.
patent: 2003/0016734 (2003-01-01), Blake
patent: 2003/0034849 (2003-02-01), Sanduleanu
patent: 2003/0074511 (2003-04-01), Kramer et al.
patent: 2004/0071389 (2004-04-01), Hofmeister et al.
patent: 10150536 (2003-04-01), None
U.S. Appl. No. 10/619,578, filed Jul. 14, 2003, Sutioso et al.

Affiliated with

Also associated with

Rating

Architectures, circuits, systems and methods for reducing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Architectures, circuits, systems and methods for reducing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Architectures, circuits, systems and methods for reducing... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4103995