Architecture with centralized single memory for the transfer of

Television – Basic receiver with additional function – For display of additional information

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Details

348714, 348715, 348716, 348722, 345509, 345521, H04N 546

Patent

active

06133961&

DESCRIPTION:

BRIEF SUMMARY
The present invention relates to an architecture with multiple input and output paths allowing the storage and transfer of still or moving video images.
More particularly, the invention relates to a novel architecture allowing real-time implementation of the operations mentioned above (transfer, storage) while complying with "Broadcast" quality for the digital video images. "Broadcast" quality should be understood to mean, for example, a representation of the data in the 4:2:2:4 format on 10 bits.


DESCRIPTION OF THE INVENTION

According to the known art, the storage of the video images is carried out with the aid of special-purpose memories, termed "frame memories", better known to those skilled in the art as "frame buffers".
A "frame buffer" is a physically localized memory intended for the video function and specially adapted to the video format for which it was designed. If it is desired to work with several video paths, the information storage system must then be equipped with several special-purpose memories so that to each video path there corresponds a special-purpose memory. If it is desired to have access to a large quantity of information, it is then necessary to multiply up the number of "frame buffers".
Momentary reduced use of the number of video paths then leads to partial utilization of the "frame buffers". This represents a drawback.
Conversely, it is impossible to work in real time on a large number of paths such as, for example, a number of paths equal to 8.
The invention does not have these drawbacks.


SUMMARY OF THE INVENTION

The present invention relates to an architecture making it possible to store and transfer still or moving digital video images, the said architecture comprising at least one input circuit allowing access for data intended to make up a video image, a memory area making it possible to store video images, at least one output circuit making it possible to extract at least one video path from the said architecture and a video bus intended to provide for the transfer of information between the memory area, the input circuit and the output circuit, characterized in that the memory area is a general-purpose memory and in that the video bus has a width greater than or equal to the width of the memory area.
The input circuit allowing access for data intended to make up a video image may be a straightforward video input. It may also be an input making it possible to draw video animations, or else an input of the "bit map" file type.
According to the invention the video frames constituting the various video paths are stored in a single general-purpose memory. "General-purpose" memory should be understood to mean a memory no part of which is particularly dedicated to a path. Depending on the required use, this memory can contain a number of units with several million frames or images. Advantageously the architecture according to the invention allows the simultaneous use of several paths, it being possible for each of them to be constituted by any sequence of frames available in the memory. It is then possible to modify, insert or delete frames in any sequence whatsoever. The output from the system thus obtained can also be recorded in the single memory and become in turn a source sequence.
With the exception of the video formatting/deformatting sub-assemblies, the system is advantageously independent of the dimension of the images, of the scanning system and of the frequencies of the video standard used at output.


BRIEF DESCRIPTION OF THE DRAWINGS

Other characteristics and advantages of the invention will emerge on reading a preferred embodiment given with reference to the appended figures in which:
FIG. 1 represents a basic diagram of the architecture according to the invention;
FIG. 2 represents a first application of the architecture according to the invention;
FIG. 3 represents a detail of the architectures of FIGS. 1 and 2;
FIGS. 4 and 5 represent 2 different embodiments of a second application of the architecture according to the invention.
In all these figures, th

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patent: 5680156 (1997-10-01), Gove et al.
patent: 5706290 (1998-01-01), Shaw et al.
patent: 5784047 (1998-07-01), Cahill, III et al.

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