Architecture to implement floating point multiply/accumulate ope

Details Architecture to implement floating point multiply/accumulate ope Architecture to implement floating point multiply/accumulate ope

1987-10-05

1989-06-20

Malzahn, David H.

Boots, shoes, and leggings

G06F 738

Patent

active

048414670

ABSTRACT:
A multiply/accumulator chip architecture capable of operating at a 20 megahertz system clock rate is designed so as to accept floating point numbers in sign magnitude form, to compute a product of the fractional portions thereof and to convert the fractional result into two's complement form for accumulation with the results of a previous product. This architecture readily permits the computation of vector-type inner product operations in a high speed pipelined fashion. Additionally, leading zero's and leadings one's detection is carried out in a multiply parallel fashion so as to rapidly produce post normalization results from the additive portion of the system. The system is implementable on a single integrated circuit chip in which an array multiplier is present so as to minimize inter-chip delays. The architecture of the present invention provides a high speed floating point multiply and accumulate operation with a short pipeline latency.

REFERENCES:
patent: 4511990 (1985-04-01), Hagiwara et al.
patent: 4589067 (1986-05-01), Porter et al.
patent: 4683547 (1987-07-01), DeGroot
Earle et al., "Exponent Differences and Preshifter", IBM Technical Disclosure Bulletin, vol. 9, No. 7, Dec. '66, pp. 848-849.
Sproul, "High-Speed Floating-Point Accumulator", IBM Tech. Disclosure Bulletin, vol. 14, No. 10, Mar. 72, pp. 2934-2936.
"An IEEE Standard Floating Point Chip", A. Komal, K. Goskel, Phil W. Diodato, John A. Fields, Ulhas V. Gumaste, Chaw K. Kung, Kingyao Lin, Mario E. Lega, Peter M. Maurer, Thomas K. Ng, Yaw T. Oh, Mark E. Thierbach-AT&T Bell Labs., 1985, IEEE Intnl. Solid-State Circuits Conf.-Feb. 13, 1985, pp. 18-19.
"A Single Chip 80b Floating Point Processor"-Karumitsu Takeda, Fumiaki Ishino, Yoshitaka Ito, Ryota Kasai, Takayoshi Nakashima, NTT Atsugi Electric Comm. Lab.-1985 IEEE Intnl. Solid-State Circuits Conf.-pp. 16-17.
"An NMOS 64b Floating-Point Chip Set"-William M. McAllister, Dan Zuras, Hewlett-Packard Co., 1986 IEEE Intnl. Solid-State Circuits Conf.-Feb. 19, 1986, pp. 34-35.
"A 32b Floating Point CMOS Digital Signal Processor", Yuichi Kawakami, Hideo Tanaka, Tomoji Nukiyama, Makoto Yoshida, Takeo Nishitani, Ichiro Kuroda, Minoru Araki, Ioshiaki Hoshi-NEC Corp., Kawasaki, Japan, 1986 IEEE Intnl. Solid-State Cir. Conf., Feb. 19, 1986-pp. 86-87.
"A 64b Floating Point Processor"-Frederick A. Ware, Hewlett-Packard Co.-1982 IEEE International Solid-State Circuits Conf.-pp. 24-25.

Affiliated with

Also associated with

Rating

Architecture to implement floating point multiply/accumulate ope does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Architecture to implement floating point multiply/accumulate ope, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Architecture to implement floating point multiply/accumulate ope will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-530140