Architecture of transfer processor

Details Architecture of transfer processor Architecture of transfer processor

1994-03-08

1996-06-04

Geckil, Mehmet

Boots, shoes, and leggings

39542102, 364DIG1, 364228, 364229, 3642318, 364243, 3642434, G06F 1300

Patent

active

055242650

ABSTRACT:
This invention is a data processor including a data transfer controller. The data transfer controller includes internal and external memory interfaces coupled to internal and external memory, respectively. A pipeline controller controls the internal memory interface and the external memory interface. A source address generator generates addresses for reading data. A destination address generator generates addresses for writing data. Buffer circuitry interposed between the source address generator and the destination address generator permits data to be aligned to differing source and destination data word sizes and differing data word boundaries. An external sequencer provides control signals for the external memory via the external memory interface. In the preferred embodiment, the buffer circuitry includes a first-in-first-out (FIFO) buffer having a plurality of registers. This permits continued operations in many cases when either the source or destination memory operations temporarily stall. The buffer circuitry preferably is used for buffering processor requested data transfers. Also a further cache buffer having a plurality of registers is used in buffering instruction cache service requests. The data transfer controller includes refresh registers coupled to the external sequencer. This provides data refreshing of dynamic random access memories. The data transfer controller further includes request prioritization circuitry coupled to the pipeline controller for prioritization of data transfer requests to the pipeline controller.

REFERENCES:
patent: 4446514 (1984-05-01), Brown et al.
patent: 4491907 (1985-01-01), Koeppen et al.
patent: 4517656 (1985-05-01), Solimeno et al.
patent: 4639765 (1987-01-01), D'Hont
patent: 4656597 (1987-04-01), Bond et al.
patent: 4665495 (1987-05-01), Thaden
patent: 4694391 (1987-09-01), Guttag et al.
patent: 4718024 (1988-01-01), Guttag et al.
patent: 4769640 (1988-09-01), Sato
patent: 4821187 (1989-04-01), Ueda et al.
patent: 5197140 (1993-03-01), Balmer
patent: 5212777 (1993-05-01), Gove et al.
patent: 5226125 (1993-07-01), Balmer et al.
patent: 5237686 (1993-08-01), Asano et al.
patent: 5239654 (1993-08-01), Ing-Simmons et al.
Microprocessor Report, Slater, Michael, "IIT Ships Programmable Video Processor," vol. 5, No. 20 Oct. 30, 1991 pp. 1, 6-7, 13.

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