Architecture of circuitry for generating test mode signals

Details Architecture of circuitry for generating test mode signals Architecture of circuitry for generating test mode signals

1991-11-12

1994-08-16

Atkinson, Charles E.

Excavating

365201, G01R 3128

Patent

active

053393201

ABSTRACT:
An arrangement for generating signals for generating a particular set of test conditions within a digital circuit including a plurality of latches for storing individual bits of data representing individual operations to be accomplished within the digital circuitry, the latches each having input and output terminals; the output terminals of each of the latches being connected to individual portions of the digital circuitry to effect an individual operation thereby; apparatus connected to the input terminals of the latches for setting individual selected ones of the latches to provide selected test conditions; and apparatus for transferring the condition of a selected number of the latches simultaneously to effect a selected test condition.

REFERENCES:
patent: 5115435 (1992-05-01), Langford, II et al.
patent: 5245577 (1993-09-01), Duesman et al.

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