Architecture of a parallel computer and an information...

Electrical computers and digital processing systems: processing – Instruction issuing

Reexamination Certificate

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C712S034000

Reexamination Certificate

active

10088028

ABSTRACT:
A computer system provides distributed memory computer architecture achieving extremely high speed parallel processing, and includes: a CPU modules, a plurality of memory modules, each module having a processor and RAM core, and a plurality of sets of buses making connections between the CPU and the memory modules and/or connections among memory modules, so the various memory modules operate on an instruction given by the CPU. A series of data having a stipulated relationship is given a space ID and each memory module manages a table containing at least the space ID, the logical address of the portion of the series of data managed, the size of the portion and the size of the series of data, and, the processor of each memory module determines if the portion of the series of data managed is involved in a received instruction and performs processing on data stored in the RAM core.

REFERENCES:
patent: 5490260 (1996-02-01), Miller et al.
patent: 5822785 (1998-10-01), Ikeda et al.
patent: 5829041 (1998-10-01), Okamoto et al.
patent: 6226738 (2001-05-01), Dowling
patent: RE37305 (2001-07-01), Chang et al.
patent: 1121015 (1982-03-01), None
patent: 0 408 810 (1991-01-01), None
patent: 54-56743 (1979-05-01), None
patent: 62-022142 (1987-01-01), None
patent: 63-316254 (1988-12-01), None
patent: 06-067846 (1994-03-01), None
patent: 07-152640 (1995-06-01), None
patent: 10-143489 (1998-05-01), None
patent: 11-263793 (1999-09-01), None
John L Hennessy and David A Patterson, Computer Organization and Design the Hardware/Software Interface, 1998, Morgan Kaufmann Publishers, 2nd Edition, pp. 16-18, 541, and 712-713.
Rosenberg, J , Dictionary of computers, information processing & telecomunications 2ndEd, Pub. James Wiley & Sons 1987 pp. 451.
European Search Report, Nov. 21, 2002 date of completion.
Ananthanarayanan R et al, “Experiences in Integrating Distribution Shared Memory With Virtual Memory Management” Operating Systems Review (SIGOPS), ACM Headquarter, New York, US, vol. 26, No. 3, Jul. 1, 1992, pp. 4-26.
Joho Shori, vol. 32, No. 12, Dec. 1991, “Kinou Memory ni yoru Chou Heiretsu Shori”, Hitoro YASUURA, pp. 1260-1267.

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