Architecture, method(s) and circuitry for low power memories

Details Architecture, method(s) and circuitry for low power memories Architecture, method(s) and circuitry for low power memories

2002-07-19

2004-01-06

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S226000

Reexamination Certificate

active

06674682

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to memory circuits generally and, more particularly, to an architecture, method and/or circuit for implementing a low power memory.
BACKGROUND OF THE INVENTION
Conventional memory architectures include features that waste DC and AC current consumption by one or more of the following (i) passive (no gain) static loads, (ii) large sub-wordlines, (iii) sub-wordline circuits not included in the memory array, (iv) row, column and block array partitions not included in the memory array, (v) double ended buses (address path, local and global data output path, data input path), (vi) equalization circuitry placed at one end of the memory array, (vii) address predecoders, and/or (viii) replaced defective blocks still connected to the source current.
SUMMARY OF THE INVENTION
The present invention concerns a memory array comprising at least 2 Meg of SRAM cells and configured to consume a maximum average operating current of 9.43 mA.
The objects, features and advantages of the present invention include providing a memory that may (i) reduce and/or eliminate DC current consumption, (ii) minimize rail-to-rail switching capacitance, (iii) reduce the amount of rail-to-rail switching, and/or (iv) reduce AC current consumption,


REFERENCES:
patent: 4982372 (1991-01-01), Matsuo
patent: 4985639 (1991-01-01), Renfrow et al.
patent: 5036491 (1991-07-01), Yamaguchi
patent: 5060200 (1991-10-01), Miura et al.
patent: 5119334 (1992-06-01), Fujii
patent: 5126973 (1992-06-01), Gallia et al.
patent: 5264745 (1993-11-01), Woo
patent: 5270975 (1993-12-01), McAdams
patent: 5349206 (1994-09-01), Kimura
patent: 5379257 (1995-01-01), Matsumura et al.
patent: 5389828 (1995-02-01), Tago
patent: 5438550 (1995-08-01), Kim
patent: 5555529 (1996-09-01), Hose, Jr. et al.
patent: 5581498 (1996-12-01), Ludwig et al.
patent: 5600274 (1997-02-01), Houston
patent: 5691933 (1997-11-01), Takenaka
patent: 5696463 (1997-12-01), Kwon
patent: 5818090 (1998-10-01), Kimura
patent: 5828614 (1998-10-01), Gradinariu
patent: 5841687 (1998-11-01), Rees
patent: 5872464 (1999-02-01), Gradinariu
patent: 5886937 (1999-03-01), Jang
patent: 5968190 (1999-10-01), Knaack
patent: 6118727 (2000-09-01), Allan et al.
patent: 6163495 (2000-12-01), Ford et al.
patent: 6323701 (2001-11-01), Gradinariu et al.
patent: 6378008 (2002-04-01), Gradinariu
Practical Digital Design Using ICs, 3rd Edition, by Joseph D. Greenfield, 1994, pp. 416-433.
Memory 1996, by Jim Griffin, Brian Matas and Christian de Subercasaux, 1996, pp. 7-1 to 10-10.
Session 16: Dynamic RAMs, FAM 16.6: A 45ns 16Mb DRAM with Triple-Well Structure, By Fujii et al., IEEE International Solid-State Circuits Conference, 1989, pp. 248-249.
FA 13.5: A 15ns 16Mb CMOS SRAM with Reduced Voltage Amplitude Data Bus,By Matsumiya et al., IEEE International Solid-State Circuits Conference, 1992, pp. 214-216.

Affiliated with

Also associated with

Rating

Architecture, method(s) and circuitry for low power memories does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Architecture, method(s) and circuitry for low power memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Architecture, method(s) and circuitry for low power memories will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3227113