Architecture for very high-speed decision feedback sequence...

Details Architecture for very high-speed decision feedback sequence... Architecture for very high-speed decision feedback sequence...

2007-02-13

2007-02-13

Corrielus, Jean B. (Department: 2611)

Pulse or digital communications

Equalizers

Automatic

C375S262000, C375S341000

Reexamination Certificate

active

09804082

ABSTRACT:
A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.

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