Architecture for switching packets in a high-speed switching...

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

Reexamination Certificate

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C370S429000, C370S388000

Reexamination Certificate

active

10360094

ABSTRACT:
A system for switching packets in a high-speed switching environment includes one or more memory structures, multiple input structures that can each write to each of the one or more memory structures, and a first switching structure that couples the input structures to the one or more memory structures. The system also includes multiple output structures that can each read from each of the one or more memory structures and communicate a first portion of a packet to a first component of a communications network before an input structure has received a second portion of the packet from a second component of the communications network. The system also includes a second switching structure that couples the plurality of output structures to the one or more memory structures. The second switching structure is coupled to the one or more memory structures by a first number of links and coupled to the plurality of output structures by a second number of links, and the first number of links is twice or more the second number of links.

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Cyriel Minkenberg and Ton Engbersen, “A Combined Input and Output Queued Packet-Switched System Based on PRIZMA Switch-on-a Chip Technology,” IEEE Communications Magazine, pp. 70-77, Dec. 2000.
James P. G. Sterbenz and Joseph D. Touch, “High-Speed Networking,” 5 pages, 2001.
Abhijit K. Choudhury and Ellen L. Hahne, “Dynamic Queue Length Thresholds for Shared-Memory Packet Switches,” IEEE/ACM Transactions on Networking, vol. 6, No. 2, pp. 130-140, Apr. 1998.
M. Shreedhar and George Varghese, “Efficient Fair Queuing using Deficit Round Robin,” pp. 1-21, Oct. 16, 1995.

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