Architecture for programmable delay line integrated circuit

Details Architecture for programmable delay line integrated circuit Architecture for programmable delay line integrated circuit

1992-05-28

1994-10-11

Callahan, Timothy P.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307605, 307608, 328 55, H03K 5159, H03K 301

Patent

active

053550382

ABSTRACT:
A programmable delay line with digital input to a two-part digital-to-analog converter structure to define an equivalent resistance at a pull-down node. Preferred embodiments are configured as two identical halves. The outputs of the two halves are combined to produce an exactly symmetrical waveform. This is particularly advantageous in a programmable delay line, since this architecture assures that control changes which change the delay will not also introduce asymmetry into the output waveform.

REFERENCES:
patent: 4866314 (1989-09-01), Traa
patent: 5063311 (1991-11-01), Swapp
patent: 5144174 (1992-09-01), Murakami
patent: 5159205 (1992-10-01), Gorecki et al.
patent: 5175452 (1992-12-01), Lupi et al.
patent: 5192886 (1993-03-01), Wetlaufer

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