Architecture for power of two coefficient FIR filter

Details Architecture for power of two coefficient FIR filter Architecture for power of two coefficient FIR filter

1986-12-18

1988-11-01

Harkcom, Gary V.

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G06F 1531

Patent

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047824581

ABSTRACT:
An architecture for a very large scale integrated (VLSI) implementation of a finite imprise response (FIR) digital filter having no multipliers and a coefficient space limited to powers of two. The filter structure includes a data bus, a coefficient bus and a sum-in bus to each coefficient tap. Each tap has a coefficient and control word register which is loaded during an initialization phase of the filter. Multiplication is provided by a shifter which provides the correct power of two weighting of an input data sample. The weighted data sample at each tap is added to the output of the previous tap. This architecture results in a regular, modular structure which can be cascaded and which is programmable for various data word lengths and coefficient spaces.

REFERENCES:
patent: 3860892 (1975-01-01), Speiser et al.
patent: 3979701 (1976-09-01), Tomozawa
patent: 4322810 (1982-03-01), Nakayama
patent: 4356558 (1982-10-01), Owen et al.
patent: 4507725 (1985-03-01), Christopher et al.
patent: 4524423 (1985-06-01), Acampora
patent: 4700345 (1987-10-01), Morcom et al.

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