Architecture for modular computer system in which one of the mod

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395672, G06F 900

Patent

active

058420134

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

Large amounts of data are handled by the user interface of computers. Data take up a considerable quantity of the computer's throughout, because on one hand the resolution of imaging systems is increasing constantly and new applications such as animation and desktop video require high data transfer rates for structured or unstructured graphics, and on the other hand, with the constantly growing complexity of operating structures, shorter response times are being demanded from inter-active systems.
It is an established fact that not only the main processor in the computer but also, if necessary, additional passive or active components are used in order to generate the presentations made accessible to a human being by the imaging system (see: Foley, van Dam, Feiner, Hughes, "Computer Graphics, Principles, and Practice", 2nd edition, Addison-Wesley Publishing Company, Reading, Mass., ISBN 0-201-12110-7, and in the following especially EP 0350911 A2 for a service processor).
Present-day systems do not take account in their structures of the extreme demands that have to be met in order to achieve the operational functionality of the user interface, nor the huge quantities of data that have to be imported from or exported to a point outside the graphics sub-system and the main processor in a very short time, e.g. from a mass storage device or an input/output interface. For instance, the image memory of a system that strives to attain a resolution of 1600.times.1200 pixels with a colour depth of 32 bits per pixel will take up about 7.5 MB. For an animation sequence running at 25 images per second, some 187 MB/second of new data will have to be imported into this memory to recreate the image displayed. If an image repeat rate of 100 Hz is the aim, however, 750 MB/s have to be read from this memory and displayed simultaneously.
This leads a severe overloading of the part of the computer installation that is supposed to be working on an actual application, meaning calculating and retaining the data and so forth. The performance of this part of the computer is severely affected both by the heavy load placed on its data paths for transporting the data to and from the graphics sub-system, which can cause a blockage of the main processor or other subordinate units (see also EP 0350911 A2 as an example of a multi-processor system in which the shared main memory of this close-coupled multi-processor system is described as the principle `bottleneck`), and,by the frequent interruptions suffered by the working procedure for the purpose of reacting instantly to an input from the user or for maintaining the actuality of the presentation. Moreover, with these kinds of architecture it is not possible to forecast their performance without limiting the availability of the system for user queries (see EP 0350911 A2, if the system support processor is occupied with handling interrupts, semaphores, etc.).


SUMMARY OF THE INVENTION

The present invention is thus based on the task of reducing the load on the parts of the computer handling the actual application caused by implementing the user interface for presentation and function, thereby in order to achieve more efficient computers with which, even if their familiar components are retained and even despite ever more stringent demands on the quality of the user interface, it will be possible greatly to increase the capacity available for the application and to achieve a good level of predictability.
According to the method of the invention the present solution consists of the architecture for a computer with a user interface along the lines of claim 1, characterised by: way that one of them, Part 1 (101), mainly takes over the function of providing the user interface in presentation and function; another, Part 2 (102), mainly operates the application programs divorced from their user interface and the operating programs needed for it; and the third, Part 3, takes charge of the remaining components (107, 108, 109, 110) of the computer; the parts not neces

REFERENCES:
patent: 4570220 (1986-02-01), Tetrick et al.
patent: 5179660 (1993-01-01), Devany et al.
Siemens-Katalog MP 29, "Proze.beta.leitsystem TELEPERM M", Aug. 1983.
Enslow, Jr., "Multiprocessors and Parallel Processing", 1974, pp. 328 th 335.
M. Conner: "Boards speed Windows and vie as standards". In: EDN Electrical Design News, Oct. 10, 1991, Newton, MA, US, pp. 97-102.

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