Architecture for high performance management of multiple circula

Details Architecture for high performance management of multiple circula Architecture for high performance management of multiple circula

1995-03-29

1996-05-21

Chin, Wellington

Multiplex communications

Wide area network

Packet switching

370 61, 370 851, 370 942, H04L 1256

Patent

active

055197019

ABSTRACT:
A queue manager manages multiple interfaces among a network, a host bus and a storage means including multiple circular FIFO's in a data communication system handling packet and multimedia data transferred, in either direction, between the host bus and the network. The queue manager includes a programmable parameter RAM interface, computation logic and status means. An efficient queue management algorithm dynamically manages storage of data in the circular multiple FIFO's as data is transferred, in either direction, between the host bus and the network. System bandwidth is allocated by the queue manager to the queues which have the most activity thereby improving the speed of transferring data while reducing the amount of bandwidth that would otherwise be required by prior systems. The programmable interface permits a user to define and dynamically configure the multiple circular FIFO storage means to include other parameters useful in the management of data transferred between the host bus and the network.

REFERENCES:
patent: 4507760 (1985-03-01), Fraser
patent: 4611322 (1986-09-01), Larson et al.
patent: 4682284 (1987-07-01), Schrofer
patent: 4807111 (1989-02-01), Cohen et al.
patent: 4816996 (1989-03-01), Hill et al.
patent: 4888739 (1989-12-01), Frederick et al.
patent: 4914652 (1990-04-01), Nguyen
patent: 4951280 (1990-08-01), McCool et al.
patent: 5043981 (1991-08-01), Firoozmand et al.
patent: 5065397 (1991-11-01), Shiobara
patent: 5119374 (1992-06-01), Firoozmand et al.
patent: 5136582 (1992-08-01), Firoozmand
patent: 5448558 (1995-09-01), Gildea et al.
Electronics OGGI, No. 97, of Mar. 31, 1990, pp. 101-109, by Emanuele Dal Lago, entitled "Quando Risc Si Unisce A Cisc".
Proceedings of SPIE, The International Society for Optical Engineering, vol. 1577 entitled "High-Speed Fiber Networks & Channels," held Sep. 1991, pp. 86-96, by R. Venkataraman, article entitled Designing a VMEbus FDDI Adaptor Card`.
Digital Technical Journal, vol. 3, No. 2, Spring 1991, by W. R. Hawe et al., pp. 10-18, entitled "Fiber Distributed Data Interface Overview".
IBM Technical Disclosure Bulletin, vol. 24, No. 6, Nov. 1981, pp. 2716-2723, by E. D. Conroy, entitled "Hardware/Microcode Support of Queuing".

Affiliated with

Also associated with

Rating

Architecture for high performance management of multiple circula does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Architecture for high performance management of multiple circula, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Architecture for high performance management of multiple circula will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2044794