Architecture for high bandwidth wide I/O memory devices

Details Architecture for high bandwidth wide I/O memory devices Architecture for high bandwidth wide I/O memory devices

1998-12-22

2000-02-22

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 36523004, G11C 800

Patent

active

060288116

ABSTRACT:
A random access memory (RAM) (700) is disclosed which includes a reduced page size for decreasing power consumption, and a unique input/output (I/O) arrangement for maintaining a relatively large I/O space, without substantially increasing the number of I/O lines within the RAM. The RAM (700) includes a number banks (704) each of which is logically divided into even array sections and odd array sections (900). Data from the array sections (900) is coupled to I/O select blocks (914, 916, 918, 920) by groups of local I/O lines (902, 904, 906, 908). According to an applied address, the sense amplifiers within the even array sections are activated, indicating an "even" sense cycle, or the sense amplifiers within the odd array sections are activated, indicating an "odd" sense cycle. In an even sense cycle, the I/O select blocks (914, 916, 918, 920) couple the LIO line groups of the even array sections (900) to global I/O lines (910, 912). In an odd sense cycle, the I/O select blocks (914, 916, 918, 920) couple the LIO lines groups of the odd array sections (900) to global I/O lines (910, 912).

REFERENCES:
patent: 5594704 (1997-01-01), Konishi et al.
patent: 5617555 (1997-04-01), Patel et al.
patent: 5928373 (1999-07-01), Yoo

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