Architecture for hard disk drive write preamplifiers

Details Architecture for hard disk drive write preamplifiers Architecture for hard disk drive write preamplifiers

1999-03-31

2001-01-16

Kim, W. Chris (Department: 2753)

Dynamic magnetic information storage or retrieval

General recording or reproducing

Specifics of the amplifier

C360S046000, C327S110000

Reexamination Certificate

active

06175463

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
The present invention is related to an invention that is the subject matter of a commonly-assigned co-pending application entitled “Voltage Boost Circuitry For Hard Disk Drive Write Preamplifiers”, filed concurrently herewith, which is incorporated by reference herein and is also related to an invention that is the subject matter of a commonly-assigned co-pending application entitled “Fast High Side Switch for Hard Disk Drive Preamplifiers”, also filed concurrently herewith, also incorporated by reference herein.
1. Field of the Invention
The present invention relates generally to an architecture for hard disk drive write preamplifiers, and, more particularly, to an architecture for increasing the rise-time, i.e., the time that it takes the current in a hard disk drive write head to be reversed, by boosting the supply voltage only when it is needed, and also, so as to compensate for the delay in engaging boost voltage, an architecture which will delay the data signals by the same amount of time that it takes to engage the boosting value.
2. Background of the Invention
Write speeds in hard disk drive preamplifiers are continually improving. An inductive write head includes an inductive coil that can change the localized magnetic fields on the magnetic data-storage medium and thus allows the digital data to be recorded. The speed of this recording process (i.e., the write speed) is determined by how fast the current in a hard disk drive write head can be reversed (the polarity of the write current through the write head being reversed in response to the bit pattern of the information signal). This is also referred to as the “rise-time”. Typically, the desired requirements for the write driver are a large current capability (e.g., 40-80 ma) combined with a fast rise time (e.g., 1-4 ns) for driving the inductive write head.
The write head for a disk data storage device can be approximately modeled by an inductor with an inductance of L. The voltage across an inductor is ideally proportional to the rate of change of the current through the inductor in time. The mathematical expression for this voltage is given as V
L
=L di/dt. Essentially, the voltage across the inductive write head, V
L
, is proportional to the value of inductance, L, and to the speed at which the write current is reversed, di/dt. This means that the write current reversal time in inductive write-heads fundamentally depends on how large a voltage can be impressed across the write drive head. Normally, the voltage across the inductor is limited by the supply voltages. Thus, either the head inductance value should be decreased, or, the supply voltage should be increased, to improve the write speed. The first option, decreasing the head inductance value, is normally not preferred, as it negatively affects the reliability of the data-recording process.
Conventional techniques use the power supply to generate the voltage across the inductor. However, the voltage supply limits the voltage that can be applied across the inductor and therefore limits the rise time. Higher write speeds require higher supply voltages. However, the second alternative, increasing the supply voltage, may not always be possible, as system-wide considerations dictate the selection of power supply voltages, and the present trend in fact is the reduction of power supply voltages.
A simplified diagram of an inductive write head with current switching circuitry is shown in
FIG. 1. A
standard H-bridge is used to drive the write head, which is modeled by the inductor L
1
. The arrangement shown in
FIG. 1
is known as an “H-bridge” or an “H-switch” because the four switches, or commonly transistors (operating between conductive (activated) and non-conductive states as switches), and the inductor, operate in an “H-like” formation. In particular, one pair of switches direct current flow in a first diagonal direction through the inductor and the other pair directs current flow in a second opposite diagonal direction through the inductor.
The write-head is connected to first and second write terminals of the H-Bridge (T
1
and T
2
of FIG.
1
). Transistors Q
2
and Q
4
have their collectors connected to voltage source V
CC
and their emitters connected to the respective collectors of transistors Q
1
and Q
3
. The emitters of transistors Q
1
and Q
3
are then coupled together and coupled to ground. When the “Data” line to transistors Q
2
and Q
3
(which form a first diagonal pair) is high, “Data_bar” is low, and transistors Q
4
and Q
1
(which form a second diagonal pair) are low. Accordingly, the first diagonal pair conducts current causing inductor L
1
to have a first polarity, i.e., the collector of transistor Q
2
is at V
CC
(e.g., 5 volts) and the emitter of transistor Q
2
, i.e., T
1
, is slightly below that (e.g., 4.4 volts). Transistor Q
3
is pulled high, and point T
2
is pulled down to approximately 0 volts. Therefore, the current flows from the first write terminal T
1
(at 4.4 volts) to the second write terminal T
2
(at approximately 0 volts) through the inductor L
1
. This can be called “state
1
”.
Reversing the polarity across inductor L
1
entails deactivating the first diagonal pair, Q
2
and Q
3
, and activating the second diagonal pair, Q
1
and Q
4
, by switching inputs “Data” and “Data_bar” from high to low and low to high, respectively. Specifically, when the “Data” line goes low, and “Data_bar” goes high, transistors Q
2
and Q
3
turn off and transistors Q
1
and Q
4
turn on. Eventually, the current flows in the other direction, from the second write terminal T
2
to the first write-terminal T
1
, which can be similarly called “slate
2
”, thus generating a field having a second polarity, opposite to the first. This enables the inductive coil L
1
to write a specific bipolar magnetic pattern on a magnetic medium.
However, the current in inductor L
1
does not change instantaneously. Because “Data_bar” is pulled high, terminal T
1
is essentially pulled to ground, and transistor Q
3
is now “off”. Therefore, terminal T
2
should flow infinitely high. However, stray capacitances do not allow that to happen, for example, bipolar junction transistors have parasitic base to collector (BTC) capacitances that preclude instantaneous changes between conductive (activated) and nonconductive states and prevents the voltage at T
2
from flying high.
In order to reverse the current flow from “T
1
to T
2
” to “T
2
to T
1
” very quickly, the voltage at terminal T
2
must be made greater than the voltage at terminal T
1
. As noted above, when “Data_bar” is pulled high, terminal T
1
is pulled to ground, and it is desired to change the voltage at terminal T
2
to as high a voltage as possible, as quickly as possible.
The H-bridge circuit shown in
FIG. 2
, also conventional, provides a more practical approach. Again, when the “Data” line is high, transistors Q
2
and Q
3
are ON, therefore, the write current flows from the first write terminal (T
1
) to the second write terminal (T
2
) through the write head, modeled by inductor L
1
. The voltages at both write terminals, T
1
and T
2
, are one diode drop (V
be
) (due to diodes D
1
and D
2
) below supply voltage V
CC
. When the “Data” line goes low, transistors Q
2
and Q
3
shut off, “Data_bar” goes high, and transistors Q
1
and Q
4
turn on. However, the inductor current cannot change instantaneously, therefore the first write terminal T
1
of the write head L
1
is pulled low (note that this voltage is limited by a clamp (not shown) so that transistor Q
1
does not enter into deep-saturation). At this point, the inductor L
1
dumps its current into diode D
2
. This condition produces a voltage drop across the inductor L
1
of approximately V
CC
+V
be
−V
ce,sat
. This voltage drop determines the rate at which the inductor current decreases. When the inductor current reaches zero (0), the diode D
2
turns off and the voltage across the inductor L
1
becomes V
CC
−V
ce,sat
. Therefore, although diodes D
1
and D
2
pro

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