Architecture for efficient pattern match operations

Details Architecture for efficient pattern match operations Architecture for efficient pattern match operations

2004-05-13

2008-12-09

Cottingham, John (Department: 2167)

Data processing: database and file management or data structures

Database design

Data structure types

C707S793000, C711S108000

Reexamination Certificate

active

07464088

ABSTRACT:
A system architecture optimized for pattern match applications is provided. This system architecture includes a host computer and a pattern match accelerator (PMA), which in turn includes one or more pattern match units (PMUs) and PMU control logic. The PMU control logic can divide a database, transmitted by the host computer, such that each of the PMUs receives a database portion. Each PMU includes a main memory for storing the database portion and a programmable logic device (PLD). The PLD can perform a search and score operation on its database portion. Advantageously, the PLD can be configured to generate an index of the database portion, and then configured to perform the search and score operation using that index. The PMU control logic can assemble the results of the pattern match application from each of the PMUs.

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