Architecture for data processor

Details Architecture for data processor Architecture for data processor

1978-09-25

1982-04-20

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 916

Patent

active

043262473

ABSTRACT:
A data processor having an internal address bus and a separate internal data bus which are selectively coupled to an external memory bus. The external memory bus is time shared so that it can carry memory addresses as well as data. A command shift register, at least one capture register, a timer register, a compare register, a control register, and a status register are all coupled to the internal data bus. The command shift register is capable of serially shifting data, upon command, to an output terminal. The at least one capture register is capable of being loaded from the timer register whenever a transition occurs on a predetermined input to the data processor thereby capturing the time at which the transition occurred. The compare register is used to store a digital signal equivalent to some desired time. The compare register is continuously compared for equality with the timer register and provides a signal when equality exists. The control register is capable of providing software control of preselected registers within the data processor and the status register is used to temporarily store data indicating causes of interrupts.

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