Architecture for an improved performance of a programmable logic

Details Architecture for an improved performance of a programmable logic Architecture for an improved performance of a programmable logic

1988-12-30

1990-05-29

Malzahn, David H.

Boots, shoes, and leggings

307465, H03K 19177

Patent

active

049300970

ABSTRACT:
A programmable logic device in which memory cells are removed from the signal path. Input signals are coupled to an inverting and non-inverting buffer, wherein the memory cells are coupled to enable the buffers. The stored state of each of the memory cells determines if a corresponding buffer is to be activated. In one embodiment, a memory cell is provided for each buffer and the output of each pair of complementary buffers is coupled together to provide an output. In another embodiment, the outputs of each pair of complementary buffers are inputted to a multiplexer, wherein a corresponding memory cell coupled to its multiplexer controls the selection of the signal or its complement to be outputted.

REFERENCES:
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.

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