Architecture for an algorithmic analog-to-digital converter

Details Architecture for an algorithmic analog-to-digital converter Architecture for an algorithmic analog-to-digital converter

2006-06-27

2006-06-27

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C327S158000, C713S500000

Reexamination Certificate

active

07068202

ABSTRACT:
An algorithmic analog-to-digital converter (ADC) includes a sample-and-hold circuit and an ADC processing unit operating in parallel and sharing a single operational amplifier. The ADC processing unit includes an MDAC with a switched capacitor topology and a sub-ADC. The ADC processing unit is clocked by an internal clock that is N times faster than the sample-and-hold clock. Each cycle is further sub-divided into two phases. During one phase the capacitors are coupled to a residue or sampled voltage provided by the MDAC, and during another phase the capacitor are coupled to a reference voltage determined by the switch control signals generated by the sub-ADC. A set of data bits is generated by the ADC processing unit during each ADC clock cycle. The N sets of data bits are added to generate the digital output stream.

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