Television – Basic receiver with additional function – For display of additional information
Reexamination Certificate
1998-08-04
2003-01-28
Hjerpe, Richard (Department: 2774)
Television
Basic receiver with additional function
For display of additional information
C348S589000
Reexamination Certificate
active
06512553
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits; and, in particular, the present invention relates to integrated circuit for driving a video display.
2. Discussion of the Related Art
A monitor used in a computer system is often equipped with a on-screen menu system to provide an “on-screen display” (“OSD”) of one or more menus, showing current settings or functions of the monitor. When such a menu is displayed, an OSD window is typically created which interrupts or overlays at least a portion of the visible screen area of the video display. To achieve this overlay function, the video preamplifier is provided with a blanking capability which, when activated, inserts the OSD data in place of the video data while the video data is blanked.
FIG. 1
is a block diagram of a single-channel video preamplifier
100
in the prior art. As shown in
FIG. 1
, an analog signal representing one of the three color input signals or “channels” (R, G or B) is provided at terminal
101
as an input signal to video preamplifier
100
. This analog signal is then amplified by an input amplifier
102
. The amplified signal output of input amplifier
102
is then attenuated by video contrast attenuator
103
in accordance with a contrast attenuation signal at terminal
113
under user control. This contrast attenuation signal is typically provided externally and is common to all three channels. The contrast-attenuated signal is then adjusted in drive attenuator
104
in accordance with a channel-specific control signal at terminal
114
. The output signal of drive attenuator
104
at terminal
116
is then amplified in output amplifier
105
. The output signal at terminal
115
of output amplifier
105
is limited by an output signal of amplifier
106
(“clamp comparator”) in response, when an external clamp signal at terminal
107
is asserted, to an externally imposed cutoff voltage at terminal
108
. An external clamping capacitor (not shown) is provided coupled between terminal
109
and a reference voltage, typically ground or a supply voltage, to impose at terminal
109
a DC offset voltage to the output video signal at terminal
110
. The attenuated video signal at terminal
116
is summed in amplifier
111
with the DC offset voltage at terminal
109
, to provide at terminal
110
a video output signal. This video output signal at terminal
110
can be grounded by a blanking signal asserted at terminal
112
. When the blanking signal at terminal
112
is asserted, i.e. the video output signal at terminal
110
is grounded, OSD data generated by an external OSD integrated circuit (not shown) is inserted at terminal
110
to provide the OSD overlay.
One disadvantage of video preamplifier
100
discussed above results from the timing and delay limitations of the blanking system, so that the quality of the on-screen display within the OSD window is compromised. In addition, in a typical high-frequency video signal path, a complex technique is necessary to inject the OSD data into terminal
110
.
FIG. 2
is a block diagram of another prior art video preamplifier
200
. To simplify description and to facilitate identification, like elements in video preamplifiers
100
and
200
are provided the same reference numerals. As shown in
FIG. 2
, in addition to the R, G or B input video signal at terminal
101
, preamplifier
200
accepts also a corresponding R, G or B OSD input signal at terminal
209
. In preamplifier
200
, the video input signal received at terminal
101
is assumed to have a predetermined maximum dynamic amplitude of one volt, measured peak-to-peak. Thus, a 2-volt reference voltage (“black DC”) is provided along with amplifiers
202
and
203
to clamp, when the signal at clamp gate terminal
107
is asserted, the input video signal at terminal
101
to a 2-volt DC offset or reference voltage. The video input signal of terminal
101
is thus provided at terminal
206
as an AC 700 mV peak-to-peak video signal superimposed on the DC offset voltage. The OSD input signal
209
, originally at 0 to 4 volts peak-to-peak, is likewise amplified and provided with a DC offset voltage by amplifier
204
, to provide an OSD input signal at terminal
207
, also as an AC video signal having a maximum amplitude of 700 mV peak-to-peak. Under control of a select signal at terminal
205
, a fast commutator or switch
201
is provided to select between the OSD input signal at terminal
207
and the video input signal at terminal
206
. As in preamplifier
100
of
FIG. 1
, video contrast attenuators
103
a
and
103
b
are each provided for attenuating the corresponding one of the input video signal at terminal
206
and the input OSD signal at terminal
207
. The remainder circuitry in preamplifier
200
, i.e. drive attenuator
104
and amplifiers
105
,
106
and
111
, function in the same manner as the corresponding elements in
FIG. 1
described above.
While video preamplifier
200
overcomes both the problem of poor quality on-screen display and the problem of complex OSD data insertion in video preamplifier
100
, video preamplifier
200
is a more complex circuit having a higher power dissipation, a larger chip size and a higher pin count. Preamplifier
200
has a higher pin count because five pins are required per channel; namely, an R, G or B video input pin, an OSD input pin, an OSD/RGB select pin, a contrast pin and drive attenuation pin are required.
SUMMARY OF THE INVENTION
The present invention provides a low pin-count low cost video preamplifier with on-screen display (OSD) capability. The OSD system of the present invention, which receives an input video signal and an input OSD video signal, includes an input stage amplifying the input video signal; (b) an OSD input circuit (i) receiving the input OSD video signal, (ii) detecting an active component of the input OSD video signal, (iii) amplifying the input OSD video signal, and (iv) asserting a blanking signal when the active component is detected. In addition, the OSD system of the present invention includes an output stage, which receives the amplified input video signal, the amplified input OSD video signal, and the blanking signal. The output stage provides the amplified input OSD video signal as an output video signal of the OSD system, when the blanking signal is asserted, and provides the amplified input video signal as the output video signal of the OSD system, otherwise.
In one embodiment, the OSD video signal includes three channels. In that embodiment, the OSD input circuit detecting as the active component the signal strength of one of the three channels, and asserts the blanking signal when the signal strength exceeds a predetermined threshold. In that embodiment, the remainder two channels are used for providing the on-screen display.
In one embodiment, the output stage includes an input circuit, which receives the amplified input video signal and the blanking signal. This input circuit of the output stage provides an output signal which (i) is maintained at a predetermined voltage, when the blanking signal is asserted, and (ii) corresponds to the amplified input video signal, otherwise. The output signal is summed in a summing circuit with the amplified OSD input video signal.
In one embodiment, the input stage of the OSD system is provided a contrast attenuator circuit, which receives the input video signal and provides a contrast-attenuated input video signal. In addition, a drive attenuator circuit which attenuates the contrast-attenuated input video signal is also provided. Further, the output stage is provided a clamp comparator circuit. Such clamp comparator circuit can be used to clamp the output video signal to a predetermined signal strength.
The present invention is better understood upon consideration of the detailed description below in conjunction with the accompanying drawings.
REFERENCES:
patent: 5177612 (1993-01-01), Nakamura et al.
patent: 5461398 (1995-10-01), Tang et al.
patent: 5475443 (1995-12-01), Kwon
patent: 5493340 (1996-02-01), Kim
pa
Dinh Duc Q
Hjerpe Richard
National Semiconductor Corporation
Stallman & Pollock LLP
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