Architecture for a tapped CCD array

Details Architecture for a tapped CCD array Architecture for a tapped CCD array

2000-05-01

2002-05-21

Flynn, Nathan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Charge transfer device

C257S217000, C257S222000, C257S231000, C257S232000, C257S239000

Reexamination Certificate

active

06392260

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to charge coupled device image sensors and specifically to structures that provide for optimized output node structures and isolation pixels in multi-tapped horizontal CCD readout registers.
2. Description of Related Art
Charge coupled devices (hereinafter CCDs) are widely used in video imaging and recording applications. For example, the architecture of a CCD video sensor may follow the form dictated by the National Television Standards Committee (NTSC) for video broadcast standards. Such CCD video sensor designs need at least 488 TV lines vertically, 500 to 800 pixels per TV line, have an optical format of {fraction (4/3)} aspect ratio, and generate field interlaced video at a frame rate of 30 Hz. CCD architectures which achieved the goals of the video format imaging requirements generally fall into two categories: Interline Transfer (ILT) or Frame Transfer (FT) image sensors.
An alternative application of a CCD sensor is industrial inspection or vision equipment. The architecture of a CCD video sensor for this application may be optimized for maximum pixel resolution, or to maximize image frame rate, or both. Often inspection cameras used to inspect moving objects (e.g., on a continuous conveyor belt or rolled goods such as rolls of cloth) employ a line scan CCD sensor where a linear CCD sensor is oriented in a direction perpendicular to the direction of movement of the object being imaged. Advanced linear CCD sensor often employ an time delay and integrate technology and are referred to as TDI CCD sensors.
In
FIG. 6
, known frame transfer sensor
10
includes imaging section
2
coupled to storage section
4
. Frame transfer sensors rely on the quick transfer of image field data from an array of photo-sensitive photo-sites in imaging section
2
where photo-charge is integrated (i.e., the imaging section) to an optically opaque analog storage array (i.e., storage section
4
), and the subsequent parallel to serial transfer of the video data through horizontal CCD readout shift register
6
(HCCD shift register) through output node structure
7
, through buffer
8
to a camera circuit. An optically opaque storage array is a storage array that is covered by an optically opaque material such as an aluminum film so that the storage array is not photo-sensitive. The rapid vertical transfer of the image data from integration of the first video field is vital since the optical input onto the imaging section of the CCD sensor is continuous (not strobed or modulated during transfer).
In
FIG. 7
, known interline transfer CCD image sensor
20
(i.e., an ILT CCD sensor) includes imaging section
12
in a plurality of columns of photo-sites, each column disposed adjacent to an optically opaque interline transfer register
14
(e.g., covered with aluminum to render the transfer register insensitive to optical input). An ILT CCD sensor generally has no optically opaque storage section as does the frame transfer sensor. In an ILT CCD sensor, optical input is integrated in photo-sites
12
and then transferred to interline transfer registers
14
. Then, during the integration of the next field of data, the field of image data in interline transfer registers
14
are parallel to serial transferred through horizontal CCD shift register
16
(HCCD shift register) through output node structure
17
, through buffer
18
to a camera circuit.
In
FIG. 8
, known time delay and integrate (TDI) linear array sensor
30
includes imaging section
22
as in a frame transfer sensor, but the imaging section is generally coupled directly to horizontal CCD readout shift register
26
, and from there through output node structure
27
, through buffer
28
to a camera circuit. Imaging section
22
includes a plurality of columns, each column including a plurality of photo-sites. In operation, a camera lens focuses the image on the TDI CCD sensor. The image, that is the optical input to the TDI CCD sensor, is moving (e.g., on a conveyor belt). Thus, an image conjugate focused on the sensor appears to be moving. A portion of the image first appears on one pixel of the TDI CCD sensor, and then appears on another pixel of the sensor. The camera and sensor are arranged so that a portion of the moving image moves in a direction from the top of a column of photo-sites to the bottom of the column. The TDI CCD sensor is clocked to transfer charge down the columns of photo-sites at a rate equal to the rate that the portion of the image moves down the column. Charge generated at a first photo-site is transferred to the next photo-site at the same time that the image portion that generated the charge at the first photo-site moves to the next photo-site. In this way photo-charge is accumulated at the photo-site under the image portion as the image portion moves down the column. Thus the name, time delay and integrate (TDI).
Two-dimensional imaging arrays (e.g., in frame transfer sensors and in interline transfer sensors) generally take a snap shot of an image. The whole photo-active array of pixels integrates photo-charge for a period of time. At the end of the integration time, the information is transferred from the sensor to an external circuit element using a parallel to serial transfer scheme. Each horizontal line of pixel data is transferred into a horizontal CCD readout shift register. The line of data is then transferred serially through an output node structure at the end of the register and then through a buffer amplifier. Generally, the data rate at which signal charge can be transferred is limited to a rate that is less than the bandwidth of the output structure and buffer amplifier.
Similarly, in a TDI CCD sensor, the last pixel in each integrating column of photo-sites (i.e., the last horizontal line) is transferred into a horizontal CCD readout shift register. The line of data is then transferred serially through an output node structure at the end of the register and then through a buffer amplifier. Generally the data rate at which signal charge can be transferred is limited by the bandwidth of the output structure and buffer amplifier.
Common to all of the above CCD architectures is that data rate defining how fast data can be removed from the sensor chip is limited by the bandwidth of the output structure and buffer amplifier. In applications where the data rate must be in excess of the buffer bandwidth, the horizontal CCD readout shift register is often partitioned into sub-registers or segments. Each sub-register or register segment will then transfer signal charge to its own separate output node structure and buffer amplifier which operates at the bandwidth limit of the output structure and buffer. The data from several buffers is then multiplexed together to reconstruct the image at a higher data rate (i.e., the single buffer data rate multiplied by the number of output structures or taps). This register architecture is known as a multi-tapped horizontal readout register (FIG.
9
).
Multi-tapped register designs require placement of an output node structure (
37
A,
37
B,
37
C and
37
D of
FIG. 9
) within an extent equal to the horizontal pitch (i.e., the pixel column spacing) of the register. For high density CCD sensor designs where the pitch is small in view of the minimum dimensions permitted by the design rules for the state of the processing technology used to make the CCD, it is difficult to position an output node structure within the register pitch such that the output node structure will have high performance (high conversion efficiency and low readout noise) while not sacrificing the performance of the horizontal register. See U.S. Pat. No. 5,608,242 entitled Variable Width CCD Register With Uniform Pitch and Charge Storage Capacity, incorporated herein by reference.
In order to increase the data rate from sensors, multi-tapped outputs in the horizontal readout section are commonly employed to allow different sections of the horizontal CCD to be read out simultaneously. Because of the space required

Affiliated with

Also associated with

Rating

Architecture for a tapped CCD array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Architecture for a tapped CCD array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Architecture for a tapped CCD array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2891642