Electrical computers and digital processing systems: multicomput – Network-to-computer interfacing
Reexamination Certificate
1998-07-28
2002-02-05
Dinh, Dung C. (Department: 2153)
Electrical computers and digital processing systems: multicomput
Network-to-computer interfacing
C370S463000, C710S002000
Reexamination Certificate
active
06345310
ABSTRACT:
CROSS REFERENCE
This application is related to Ser. No. 09/123,899 pending, entitled “ARCHITECTURE FOR A MULTI-PORT ADAPTER WITH A SINGLE MEDIA ACCESS CONTROL (MAC),” filed concurrently on Jul. 28, 1998 as assigned to the same assignee as that of the present invention.
BACKGROUND OF INVENTION
1. Field of the Invention
This invention relates to communication systems. More particularly, this invention relates to a multiple port adapter having a single MAC with a single I/O port serving all ports.
2. Description of Prior Art
Increasingly in communication systems, more and more attachment devices, e.g., telephones, fax machines, modems, etc., are coupled to a host system through a multi-port adapter usually having 24 to 32 ports and fabricated in a single Very Large Scale Integrated (VLSI) chip. Each port attaches to a Physical Layer of a communication channel and is further coupled to a Media Access Control (MAC) Unit in an adapter functioning in the Open Systems Interconnect (OSI) architecture. In one prior art embodiment, each port is serviced by an adapter chip including a single MAC unit. In another prior art embodiment, multiple copies of a single MAC design are replicated in a VSLI chip to serve the respective ports. Multiple copies of the MAC unit result in a large number of gates, hence a high cost for the chip. Moreover, MAC's designed to operate at either 10 mbps or 100 mbps use only 10% of their capability when running in the 10 mbps mode. Accordingly, a single MAC may service either one 100 mbps or 8-10 mbps ports further contributing to a large number of gates.
What is needed is a multi-port adapter fabricated as a chip having a reduced number of gates and I/O pins. Lowering the gate count reduces the cost of the chip both when it is a stand alone chip and when it is a macro integrated into a larger chip. Lowering the pin count for the chip reduces the package cost of the module incorporating the chip.
Prior art related to multi-port adapters includes the following:
U.S. Pat. No. 5,568,476 issued Oct. 22, 1996, discloses a single MAC serving multiple ports using a transmit MAC, a transmit buffer, a receive MAC, a receive buffer, a control logic for reserving storage in the buffer for transmitted and received data.
U.S. Pat. No. 5,121,390 issued Jun. 9, 1992, discloses a single chip integrated data link control device having transmit and receive paths between time channels on a high TDM data link in a host processing system for ISDN application.
U.S. Pat. No. 5,625,563 issued Apr. 29, 1997, discloses serial high speed interconnect devices integrated in semiconductor devices to reduce the number of I/O pins required for communication and control between a plurality of semiconductor devices.
U.S. Pat. No. 5,594,367 issued Jan. 14, 1997 discloses an input/output circuit within an integrated circuit, the output signal driving circuitry contains a dedicated multiplexer on the output path wherein a first and second output signal can be time multiplexed on single output pad which effectively doubles number of if output signals the integrated circuit can provide with a given number of pads.
U.S. Pat. No. 4,656,620 issued Apr. 7, 1987 discloses a logic array circuit providing outputs which are time multiplexed to provide a serial output to reduce pin count of circuit modules in a large digital system.
U.S. Pat. No. 4,486,880 issued Dec. 4, 1984 discloses an output multiplexer having a plurality of inputs and responsive to a select circuit for determining the multiplexer output.
None of the prior art discloses a multiple port adapter having a single MAC with a single I/O output port coupled to a multiplexer in a Physical Layer chip serving multiple ports coupled to individual channels in a Time Division Multiplex (TDM) communication network to reduce chip logic gates an I/O pins.
SUMMARY OF THE INVENTION
An object of the invention is an architecture for an adapter having a single Media Access Control (MAC) with a single I/O output port in a multiple port adapter.
Another object is an adapter having a single MAC with a single I/O output port and a Physical Layer device serving multiple ports in a communication network.
Another object is an adapter having a single MAC with a single I/O output port coupled to a multiplexer in a Physical Layer serving multiple port coupled to a TDM network.
Another object is an adapter and method of operation having a single MAC with a single output port coupled to a multiplexer for reduced MAC circuit count and output pins.
These and other objects, features and advantages are achieved in a single MAC coupled between a host system and a time division, multi-channel network. The single MAC has a single I/O port and includes a transmit MAC and a receive MAC path. Each path is coupled at one end to the I/O pins and at the other end to separate transmit and receive storage (FIFO) devices. A transmit state machine is coupled to the transmit MAC and transmit FIFO. A receive state machine is coupled to the receive MAC and receive FIFO. Each FIFO is coupled to a host interface and provides instructions to control logic for transmitting and receiving data between the host system and the network. A port selector is coupled to the multiplexer and to the transmit and receive state machines for selecting each port on a cyclic basis to transmit and receive data. Each state machine contains a state table having a one word entry for each port to track the status of the port. The I/O pins are coupled to a Physical Layer containing a multiplexer connected to each port serving a channel in the network through a Media Independent register. As the ports are selected by the port selector, the associated word for a port is read from the table and used to control the state machine in servicing the port. The port selector also assigns a section in the FIFO's for storing data processed or to be processed by the MACs. The transmit and receive state machines operate concurrently and determine the MAC state for servicing the port, after which the MAC state is updated and stored back into the state table. In the receive direction, the ports are serviced in a round robin fashion. In the transmit direction, data is written into the transmit FIFO as space becomes available. Control Logic means controls the transfer of data between the host system and the network and vice-a-versa when instructed by the FIFOs. The chip architecture is extendable from 10 mbps to 100 mbps and reduces the I/O pin count for the adapter and the MAC chip logic by approximately 75% compared to prior art devices.
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Allison Samuel Steven
Barker Kenneth James
Dinh Dung C.
International Business Machines - Corporation
Morgan & Finnegan , LLP
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