Architecture for a multi-port adapter with a single media...

Details Architecture for a multi-port adapter with a single media... Architecture for a multi-port adapter with a single media...

1998-07-28

2002-04-16

Patel, Ajit (Department: 2662)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S428000

Reexamination Certificate

active

06373848

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
This invention relates to communication systems. More particularly, this invention relates to a multi-port adapter having a single MAC serving all ports.
2. Description of Prior Art
Increasingly in communication systems, more and more attachment devices, e.g., telephones, fax machines, modems, etc., are coupled to a host system through a multi-port adapter usually having 24 to 32 ports and fabricated in a single Very Large Scale Integrated (VLSI) chip. Each port attaches to a Physical Layer of a communication channel and is further coupled to a Media Access Control (MAC) Unit in an adapter functioning in the Open Systems Interconnect (OSI) architecture. In one prior art embodiment, each port is serviced by an adapter chip including a single MAC unit. In another prior art embodiment, multiple copies of a single MAC design are replicated in a VSLI chip to serve the respective ports. Multiple copies of the MAC unit result in a large number of gates, hence a high cost for the chip. Moreover, MAC's designed to operate at either 10 mbps or 100 mbps use only 10% of their capability when running in the 10 mbps mode. Accordingly, a single MAC may service either one 100 mbps or 1-10 mbps ports further contributing to a large number of gates.
What is needed is a multi-port adapter fabricated as a chip having a reduced number of gates. Lowering the gate count reduces the cost of the chip both when it is a stand alone chip and when it is a macro integrated into a larger chip.
Prior art related to multi-port adapters includes the following:
U.S. Pat. No. 5,568,476 issued Oct. 22, 1996, discloses a single MAC serving multiple ports using a transmit MAC, a transmit buffer, a receive MAC, a receive buffer, a control logic for reserving storage in the buffer for transmitted and received data.
U.S. Pat. No. 5,121,390 issued Jun. 9, 1992, discloses a single chip integrated data link control device having transmit and receive paths between time channels on a high TDM data link in a host processing system for ISDN application.
U.S. Pat. No. 5,530,894 issued Jun. 25, 1996, discloses an adapter comprising a transmit and receive partitions for respectively forwarding signals in a computer system to a switch circuit and from the switch circuit to the computer circuit.
U.S. Pat. No. 5,625,563 issued Apr. 29, 1997, discloses serial high speed interconnect devices integrated in semiconductor devices to reduce the number of I/O pins required for communication and control between a plurality of semiconductor devices.
U.S. Pat. No. 5,293,375 issued Mar. 8, 1994, discloses a repeater interface controller which receives a data packet of one of a plurality of nodes from an associated segment of a Local Area Network (LAN). Each port node includes a partitioning port state machine which monitors its associated segment and partitions a segment from the repeater interface controller when the partitioning port state machine detects a collision in a predetermined number of consecutive data packets. The partitioning port state machine detects collisions in each packet from the beginning of the data packet until the end of a data packet.
U.S. Pat. No. 5,355,375 issued Oct. 11, 1994, discloses a hub controller for providing deterministic access to Carrier-Sense-Multiple-Access (CSMA) Local Area Network. The hub controller includes media control logic that can selectively raise a pseudo-carrier control signal to each port thereby inhibiting any CSMA/collision detection protocol LAN transmissions by that port. In this way, the media control logic allows the hub controller to control which of the multiple ports will be allowed to contend for access to a common internal bus within the hub controller and for how long.
None of the prior art discloses a multi-port adapter having a single MAC and multiplexer to reduce chip logic gates, each port successively coupled to a transmit and receive MAC path using a port selector to identify the port to be serviced and transmit and receive state machines, operating concurrently, to track, transmit and receive status at each port for transfer of data in both directions between a host system and a network.
SUMMARY OF THE INVENTION
An object of the invention is an architecture for a multi-port adapter having a single Media Access Control (MAC) serving all ports.
Another object is a multi-port adapter chip and method of operation having a reduced MAC circuit count.
Another object is a multi-port adapter and method of operation for tracking the status of each port in transmitting and receiving data between a host system and a network.
Another object is a multi-port adapter and method of operation for selecting a port to transmit and/or receive data between a host system and a network.
Another object is a multi-port adapter and method of operation having a single MAC and multiplexer for transferring data between a host system and a network.
These and other objects, features and advantages are achieved in a multi-port adapter chip having a single MAC coupled between a host system and a multi-channel network. The single MAC includes a transmit MAC and a receive MAC path. Each path is coupled at one end through a Media Independent Interface (MII) to a multiplexer and at the other end to separate transmit and receive storage (FIFO) devices. A transmit state machine is coupled to the transmit MAC and transmit FIFO. A receive state machine is coupled to the receive MAC and receive FIFO. The multiplexer is coupled to each port serving a channel through a register and a Physical Layer. Each FIFO is coupled to a host interface and provides instructions to control logic for transmitting and receiving data between the host system and the network. A port selector is coupled to the multiplexer and to the transmit and receive state machines for selecting each port on a cycle basis to transmit and receive data. Each state machine contains a state table having a one word entry for each port in tracking the status of the port. As the ports are selected by the port selector, the associated word for a port is read from the table and used to control the state machine in servicing the port. The port selector also assigns a section in the FIFO's for storing data processed or to be processed by the MACs. The transmit and receive state machines operate concurrently and determine the MAC state for servicing the port, after which the MAC state is updated and stored back into the state table. In the receive direction, the ports are serviced in a round robin fashion. In the transmit direction, data is written into the transmit FIFO as space becomes available. Control Logic means controls the transfer of data between the host system and the network and vice-a-versa when instructed by the FIFOs. The chip architecture is extendable from 10 mbps to 100 mbps and reduces the chip logic by approximately 75% compared to prior art devices.


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IBM Technical Disclosure Bulletin vol. 35, No. 2, Jul. 1992, p.233-239, “Architecture for High Performance Transparent Bridges”.

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