Architecture for a dual segment dual speed repeater

Details Architecture for a dual segment dual speed repeater Architecture for a dual segment dual speed repeater

2000-04-24

2001-05-08

Vincent, David R. (Department: 2661)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S445000

Reexamination Certificate

active

06229811

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to network repeaters generally and, more particularly, to a method and architecture for providing a dual segment, dual speed network repeater.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a repeater system
10
is shown implementing a port control section
12
and a port control section
14
that can each operate at different speeds. The circuit
10
also comprises a repeater core
16
and a repeater core
17
. The repeater core
16
is shown running at 10 Mbits per second and the repeater core
17
is shown running at 100 Mbits per second. The port control section
12
is shown having a speed select block
18
, a multiplexer/select block
20
and a port
22
. The port control section
14
is shown having a multiplexer/select block
32
, a speed select block
34
and a port
36
. A basic repeater segment (sometimes referred to as a repeater) comprises one of the repeater cores
16
or
17
and two or more of the ports
20
and
22
. The multiplexer/select block
20
connects the port
22
to either the repeater core
16
or the repeater core
17
. The speed select block
18
determines the speed of the port
22
and, by providing a signal to the multiplexer/select circuit
20
, connects the port
22
to the repeater core
16
or the repeater core
17
, whichever is operating at the appropriate speed. The speed select block
34
provides a similar function to the speed select block
18
by providing a signal to the multiplexer/select circuit
32
to connect the port
36
to the repeater core
16
or the repeater core
17
, whichever is operating at the appropriate speed. For example, if the port
22
operates at 10 Mbits per second, the multiplexer/select circuit
20
will connect the port
22
to the repeater core
16
, which is operating at 10 Mbits per second. Conversely, if the port
22
can operate at 100 Mbits per second, the multiplexer/select circuit
20
will connect the port
22
to the repeater core
17
, which is operating at 100 Mbits per second. While the particular repeater cores
16
and
17
may run at different speeds from each other, they generally have a fixed speed that does not vary.
If all of the ports are required to run at a single speed, load balancing is not generally possible since the ports will be configured to the same repeater core
16
or
17
. The number of repeater cores
16
and
17
may vary according to the configuration of the particular network.
SUMMARY OF THE INVENTION
The present invention concerns a method and architecture comprising a first port control section, a first repeater core, a second port control section, a second repeater core, and a logic circuit coupled to the first and second port control sections and the first and second repeater cores. The first repeater core and the second repeater core each may be configured to operate at one of a plurality of speeds. A logic circuit may be configured to couple each of the first and second ports to either the first or second repeater cores.
The objects, features and advantages of the present invention include providing a dual segment, dual speed repeater core allowing (i) a particular repeater core to operate at a number of speeds, (ii) a port to operate with a particular repeater core and (iii) a port from one repeater core to automatically switch to another repeater core.


REFERENCES:
patent: 5596575 (1997-01-01), Yang et al.
patent: 5742602 (1998-04-01), Bennett
patent: 5841985 (1998-11-01), Jie et al.
patent: 5887050 (1999-03-01), Fenske et al.
patent: 6041065 (2000-03-01), Melvin

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