Architecture for a dual segment dual speed repeater

Details Architecture for a dual segment dual speed repeater Architecture for a dual segment dual speed repeater

1997-11-13

2000-04-25

Olms, Douglas W.

Multiplex communications

Channel assignment techniques

Carrier sense multiple access

370408, H04L 12413

Patent

active

060552417

ABSTRACT:
The present invention concerns a method and architecture comprising a first circuit, a second circuit, and a logic circuit coupled to said first and second circuits. The first segment generally comprises a first repeater core configured to operate at one of a plurality of speeds and a first port. The second segment generally comprises a second repeater core configured to operate at one of a plurality of speeds and a second port. A logic circuit may be configured to couple each of the first and second ports to either the first or second repeater core.

REFERENCES:
patent: 5596575 (1997-01-01), Yang et al.
patent: 5742602 (1998-04-01), Bennett
patent: 5887050 (1999-03-01), Fenske et al.
S. Babar Raza et al., U.S.S.N. 08/970,058 Architecture for a Dual Segment Speed Repeater, filed Nov. 13, 1997.

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